scholarly journals Producing Random Bits with Delay-Line-Based Ring Oscillators

2013 ◽  
Vol 59 (1) ◽  
pp. 41-50 ◽  
Author(s):  
Mieczysław Jessa ◽  
Łukasz Matuszewski
Keyword(s):  
High Frequency ◽  
Field Programmable Gate Array ◽  
Delay Line ◽  
Statistical Tests ◽  
Ring Oscillators ◽  
Delay Element ◽  
Novel Approach ◽  
Field Programmable ◽  
Cryptographic Attacks ◽  
Delay Elements

Abstract One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

scholarly journals A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

2015 ◽  
Vol 61 (2) ◽  
pp. 199-204 ◽  
Author(s):  
Szymon Łoza ◽  
Łukasz Matuszewski ◽  
Mieczysław Jessa
Keyword(s):  
Random Number ◽  
Statistical Tests ◽  
Random Number Generator ◽  
Random Numbers ◽  
Ring Oscillators ◽  
Number Generator ◽  
Post Processing ◽  
Field Programmable ◽  
Cryptographic System ◽  
Many Sources

Abstract Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.

scholarly journals DWT Based Image Steganography with Seven Segment Display Pattern as a Key

2019 ◽  
Vol 8 (10S) ◽  
pp. 164-169 ◽  
Keyword(s):  
Field Programmable Gate Array ◽  
Image Steganography ◽  
Data Embedding ◽  
Secret Key ◽  
Novel Approach ◽  
Field Programmable ◽  
Speed Up ◽  
Gate Array ◽  
Reconfigurable Device

Steganography is one of the commanding and commonly used methods for embedding data. Realizing steganography in hardware supports to speed up steganography. This work realizesthe novel approach for generation of Key, for hiding and encoding processes of image steganography using LSB and HAAR DWT.The data embedding process is realized with seven segment display pattern as a secret key with various sizes using HAAR DWT and LSB. Maximum hiding effectiveness is also attained from this work. The same is implemented in hardware using reconfigurable device Field programmable gate array to improve the speed, area and power. The proposed work is also evaluated improved PSNR using MATLAB.

A Medical-Inspired Framework to Classify Downhole Shocks Waveforms While Drilling

2021 ◽  
Author(s):  
Justo Matheus ◽  
Maja Ignova ◽  
Darwin Amaya
Keyword(s):  
High Frequency ◽  
Field Programmable Gate Array ◽  
Clustering Algorithms ◽  
Control Unit ◽  
Navigation Systems ◽  
Heart Patients ◽  
Catastrophic Failures ◽  
Field Programmable ◽  
Signature Pattern ◽  
Electrocardiogram Signal

Abstract This paper presents a medical approach to classify shock waveforms acquired at 31,250 hertz downhole. The shock signals are treated as drilling electrocardiogram (D-ECG). The D-ECGs are processed using clustering algorithms and merged with drilling incidents to identify an arrhythmic signature pattern that can lead to catastrophic failures. In medicine, the analysis of heartbeat cycles in an electrocardiogram signal is very important for monitoring heart patients. In the drilling industry, downhole shocks are present most of the time. They are present so often that the authors introduce the concept of drilling electrocardiogram (D-ECG) based on shock waveforms acquired at high frequency. The shock module was implemented in hardware using a field programmable gate array (FPGA) and run inside the control unit of an RSS to complement the navigation systems composed. The shock acquisition and processing are performed at 31,250 Hz, providing enough bandwidth to fully reconstruct high-frequency events. A novel methodology combining field incidents with machine learning clustering algorithms is proposed to identify arrhythmic shocks signatures and whirl and bit bounce in real time, preventing failures to the BHA.

scholarly journals A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 308
Author(s):  
Mojtaba Parsakordasiabi ◽  
Ion Vornicu ◽  
Ángel Rodríguez-Vázquez ◽  
Ricardo Carmona-Galán
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Delay Line ◽  
Time Of Flight ◽  
Experimental Results ◽  
Digital Converter ◽  
Input Stage ◽  
Online Calibration ◽  
Field Programmable ◽  
Gate Array

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

scholarly journals GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Physics ◽  
2021 ◽  
Vol 4 (1) ◽  
pp. 1-11
Author(s):  
Pablo Dopazo ◽  
Carola de Benito ◽  
Oscar Camps ◽  
Stavros G. Stavrinides ◽  
Rodrigo Picos
Keyword(s):  
Parallel Algorithm ◽  
Field Programmable Gate Array ◽  
Computing Time ◽  
Scale Up ◽  
Delay Element ◽  
Optimal Paths ◽  
Field Programmable ◽  
Test Graph ◽  
Memristor Emulator ◽  
Game Changer

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

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