scholarly journals Low-power 3V single supply lock-in amplifier

Author(s):  
J. Aguirre ◽  
N. Medrano ◽  
B. Calvo ◽  
S. Celma

In extreme high noise level environments, linear filtering is not a suitable processing method and special techniques for accurately extracting sensor signal information should be considered. An interesting possibility are lock-in amplifiers (LIA), which use the phase sensitive detection technique (PSD) to take out the data signal at a specific reference frequency fo while noise signals at frequencies other than fo are rejected and do not affect significantly the measurement. Current commercial LIAs are expensive, heavy and power consuming devices, which preclude their use in portable sensing systems. Thus, this work analyses the possibility of exporting this technique to low-power low-voltage (LPLV) embedded applications. In particular, the aim is to implement a signal conditioning lock-in architecture suitable for 3V single battery-operated wireless sensor nodes. This implies to re-design all the processing elements in single supply -most reported LIAs are designed using dual power supply- and compatible with the power requirements of a wireless sensor network node. Further, looking for a compact LPLV solution, instead of a traditional sinusoidal input, a square wave input is considered, which can be directly obtained from the embedded microcontroller, thus avoiding blocks like a sinusoidal oscillator or function generator. Figure 1 shows the proposed block diagram and a photograph of the implemented device. Experimental results for signals buried in white noise, flicker noise, interference contamination and common-mode voltage contamination confirm the capability of the proposed solution to recover information from signal to noise ratios down to 24 dB with errors below 6% with an average power consumption of only 5 mW in full operation, being able to process signals with frequencies up to 43 kHz, as shown in Figure 2.

2015 ◽  
Vol 24 (09) ◽  
pp. 1550134 ◽  
Author(s):  
Seied Zaniar Hoseini ◽  
Johar Abdekhoda ◽  
Kye-Shin Lee

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.


2017 ◽  
Vol 29 (7) ◽  
pp. 1481-1499 ◽  
Author(s):  
Yu Jia ◽  
Jize Yan ◽  
Sijun Du ◽  
Tao Feng ◽  
Paul Fidler ◽  
...  

The convention within the field of vibration energy harvesting has revolved around designing resonators with natural frequencies that match single fixed frequency sinusoidal input. However, real world vibrations can be random, multi-frequency, broadband and time-varying in nature. Building upon previous work on auto-parametric resonance, this fundamentally different resonant approach can harness vibration from multiple axes and has the potential to achieve higher power density as well as wider frequency bandwidth. This article presents the power response of a packaged auto-parametric VEH prototype (practical operational volume of ∼126 cm−3) towards various real world vibration sources including vibration of a bridge, a compressor motor as well as an automobile. At auto-parametric resonance (driven at 23.5 Hz and 1 g rms), the prototype can output a peak of 78.9 mW and 4.5 Hz of −3dB bandwidth. Furthermore, up to ∼1 mW of average power output was observed from the harvester on the Forth Road Bridge. The harvested electrical energy from various real world sources were used to power up a power conditioning circuit, a wireless sensor mote, a micro-electromechanical system accelerometer and other low-power sensors. This demonstrates the concept of self-sustaining vibration powered wireless sensor systems in real world scenarios, to potentially realise maintenance-free autonomous structural health and condition monitoring.


2010 ◽  
Vol 144 (2) ◽  
pp. 400-406 ◽  
Author(s):  
A. D’Amico ◽  
A. De Marcellis ◽  
C. Di Carlo ◽  
C. Di Natale ◽  
G. Ferri ◽  
...  

2001 ◽  
Vol 36 (1) ◽  
pp. 102-109 ◽  
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz

2002 ◽  
Vol 37 (8) ◽  
pp. 1090
Author(s):  
T. Melly ◽  
A.-S. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz

2013 ◽  
Vol 760-762 ◽  
pp. 516-520
Author(s):  
Ge Sun ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  

A low voltage, low power up-conversion mixer is presented here for 2.4GHz wireless sensor networks (WSN). It was based on a double-balanced Gilbert cell type. The current-reuse technique was used to reduce the power consumption and negative-resistance compensation technique was used to improve the conversion gain. The mixer was designed in 0.18μm RF CMOS technology, and was simulated with Cadence SpectreRF. The simulation results indicate that the conversion gain is 6.37dB, the noise figure is 15.36dB and the input 1dB compression point is-10.3dBm, while consuming 1mA current for operating voltage at 1V.


2002 ◽  
Vol 37 (8) ◽  
pp. 1090-1090
Author(s):  
T. Melly ◽  
A. Porret ◽  
C.C. Enz ◽  
E.A. Vittoz

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.


Sign in / Sign up

Export Citation Format

Share Document