Impact of Gate Offset in Gate Recess on DC and RF Performance of InAlAs/InGaAs InP-based HEMTs

In this work, a set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (Ids,max) and transconductance (gm,max) increased. In the meantime, f T decreased while f max increased, and the highest f max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usage.

Comprehensive investigation on RF/analog parameters in ferroelectric tunnel FET

In this paper, the effect of ferroelectric layer thickness (tFE), coercive field (Ec), remnant polarization (Pr), and saturation polarization (Ps) on transfer characteristic is highlighted for a Ferroelectric Tunnel FET (Fe-TFET) through a commercial TCAD simulator. Further, we have reported the RF/analog parameters like transconductance (gm), output conductance (gd), gain (gm/gd), gate capacitance (Cgg), and cut off frequency (ft) for wide range of FE parameters in Fe-TFET. Improved RF/analog performance and transfer characteristic are obtained for low value of tFE, Pr, Ec, whereas, these behavior is degraded at high value of Ps.

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog applications

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Influence of Variation in Oxide layer Thickness on Analog and RF performances of SOI FinFET

In this paper, the influence of oxide (SiO2) layer thickness on the different figure of merits of a FinFET is analysed by varying the oxide layer thickness which is present between the gate and the Fin. Here, the overall thickness of the FinFET is taken to be 30nm, and the oxide (SiO2) layer thickness is changed from 0.8 nm to 3nm, and the analog, radio frequency parameters are determined for different structures. The performance parameters like drain current (ID), transconductance generation factor (TGF), transconductance (gm), output conductance (gds), parasitic capacitances like Cgs, Cgd, Cgg, cut-off frequency (fT), gain bandwidth product (GBW) and maximum frequency of oscillation (fmax) are calculated to learn the influence of variation in the FinFET oxide (SiO2) layer thickness. It is detected from the result and analysis that the drain current, output conductance, transconductance generation factor, transconductance and gain bandwidth product improve with decrement in oxide layer thickness. But as a tradeoff, the internal capacitances like Cgs, Cgd, Cgg, maximum frequency of oscillation and cut-off frequency degrade when there is a reduction in oxide (SiO2) layer thickness.

Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15nm gate Length

In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-Silicon MOSFET with Fixed Charges

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stackgraded channel double gate-Junctionless (TMGS-GCDGJL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generationfactor (TGF), early voltage, voltage gain, unity-powergain frequency ( f max ), unity-current-gain frequency ( f t ), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDGJL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gatejunctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDGJL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.

Design,Simulation And Analysis of Junction Version Multi-Fin FINFET

This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (µ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stack-graded channel double gate-Junctionless (TMGS-GCDG-JL) strained-silicon (s-Si) MOSFET with fixed charges is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of early voltage, transconductance generation factor (TGF), voltage gain, unity current gain frequency ( ft ), unity power gain frequency (fmax ), and gain transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDG-JL s-Si MOSFET has superior analog/RF performance compared to the gate stack-graded channel double gate-junctionless (GS-GCDG-JL) s-Si MOSFET. However, the proposed device has less transconductance and less output conductance in comparison with the GS-GCDG-JL s-Si MOSFET in strong inversion region, and reverse trend follows in sub-threshold region.

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N+ heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.

Design and Parametric Variation Assessment of Dopingless Nanotube Field-Effect Transistor (DL-NT-FET) for High Performance

In this paper, a dopingless nanotube field-effect transistor (DL-NT-FET) has been proposed and its performance analysis is done using a technology computer-aided design (TCAD) tool, ATLAS provided by Silvaco. The elimination of doping is brought in by the application of the charge-plasma (CP) technique. A comparative examination of transfer characteristics (I D -V GS ), transconductance (g m ), gate capacitances (C gs and C gd ), output characteristics (I D -V DS ), output conductance (g ds ), average subthreshold slope (AVSS), the threshold voltage (V t ), the ratio of on-current to off-current (I ON /I OFF ) and on-current has been made by varying the channel length (Lg), radius (R), gate work function (Φ), and temperature. Results revealed that increasing the channel length improves subthreshold slope with greater I ON /I OFF and less threshold voltage. It has been also noticed that increase in the radius of the nanotube or an increase in temperature results in just the opposite effect of that observed in the case of increasing channel length. The I OFF value increases significantly on increasing the temperature while the small degradation in the I ON has been noticed as a result of mobility degradation and velocity saturation. The I ON degrades 15% by increasing the temperature from 200K to 400K. The output conductance g ds also degrades on increasing the temperature. A proliferation of 39% is observed in the C gs at the V GS of 0.45V on increasing the channel length from 20 nm to 35 m whereas no significant changes are observed in the C gd for the same increment in the channel length.