Improving electrical performance in Ge–Si core–shell nanowire transistor with a new stripped structure

2018 ◽  
Vol 33 (9) ◽  
pp. 095004 ◽  
Author(s):  
Feng Xu ◽  
Bin Gao ◽  
Huaqiang Wu ◽  
He Qian
Keyword(s):  
Electrical Performance ◽  
Core Shell ◽  
Nanowire Transistor

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

scholarly journals Electrical performance of efficient quad-crescent-shaped Si nanowire solar cell

2022 ◽  
Vol 12 (1) ◽  
Author(s):  
Ramy El-Bashar ◽  
Mohamed Hussein ◽  
Salem F. Hegazy ◽  
Yehia Badr ◽  
B. M. A. Rahman ◽  
...  
Keyword(s):  
Conversion Efficiency ◽  
Short Circuit ◽  
Surface Recombination ◽  
Electrical Performance ◽  
Surface Recombination Velocity ◽  
Back Surface ◽  
Core Shell ◽  
Slight Reduction ◽  
The Core ◽  
Lifetime Effects

AbstractThe electrical characteristics of quad-crescent-shaped silicon nanowire (NW) solar cells (SCs) are numerically analyzed and as a result their performance optimized. The structure discussed consists of four crescents, forming a cavity that permits multiple light scattering with high trapping between the NWs. Additionally, new modes strongly coupled to the incident light are generated along the NWs. As a result, the optical absorption has been increased over a large portion of light wavelengths and hence the power conversion efficiency (PCE) has been improved. The electron–hole (e–h) generation rate in the design reported has been calculated using the 3D finite difference time domain method. Further, the electrical performance of the SC reported has been investigated through the finite element method, using the Lumerical charge software package. In this investigation, the axial and core–shell junctions were analyzed looking at the reported crescent and, as well, conventional NW designs. Additionally, the doping concentration and NW-junction position were studied in this design proposed, as well as the carrier-recombination-and-lifetime effects. This study has revealed that the high back surface field layer used improves the conversion efficiency by $$\sim$$ ∼ 80%. Moreover, conserving the NW radial shell as a low thickness layer can efficiently reduce the NW sidewall recombination effect. The PCE and short circuit current were determined to be equal to 18.5% and 33.8 mA$$/\hbox {cm}^2$$ / cm 2 for the axial junction proposed. However, the core–shell junction shows figures of 19% and 34.9 mA$$/\hbox {cm}^2$$ / cm 2 . The suggested crescent design offers an enhancement of 23% compared to the conventional NW, for both junctions. For a practical surface recombination velocity of $$10^{2}$$ 10 2 cm/s, the PCE of the proposed design, in the axial junction, has been reduced to 16.6%, with a reduction of 11%. However, the core–shell junction achieves PCE of 18.7%, with a slight reduction of 1.6%. Therefore, the optoelectronic performance of the core–shell junction was marginally affected by the NW surface recombination, compared to the axial junction.

scholarly journals Core-Shell Dual-Gate Nanowire Charge-Trap Memory for Synaptic Operations for Neuromorphic Applications

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1773
Author(s):  
Md. Hasan Raza Ansari ◽  
Udaya Mohanan Kannan ◽  
Seongjae Cho
Keyword(s):  
Recognition Accuracy ◽  
Long Term Potentiation ◽  
System Level ◽  
Core Shell ◽  
System Level Simulation ◽  
Nanowire Transistor ◽  
Term Potentiation ◽  
Neuromorphic Hardware ◽  
Dual Gate

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

scholarly journals Two-Dimensional Modeling of Silicon Nanowires Radial Core-Shell Solar Cells

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Qiang Zeng ◽  
Na Meng ◽  
Yulong Ma ◽  
Han Gu ◽  
Jing Zhang ◽  
...  
Keyword(s):  
Solar Cells ◽  
Silicon Nanowires ◽  
Light Absorption ◽  
Low Cost ◽  
Light Trapping ◽  
Electrical Performance ◽  
Core Shell ◽  
Two Dimensional ◽  
Strong Light ◽  
The Impact

Silicon nanowires radial core-shell solar cells have recently attracted significant attention as promising candidates for low cost photovoltaic application, benefit from its strong light trapping, and short radial carrier collection distances. In order to establish optics and electricity improvement, a two-dimensional model based on Shockley-Read-Hall recombination modes has been carried out for radial core-shell junction nanowires solar cell combined with guided resonance modes of light absorption. The impact of SiNWs diameter and absorption layer thickness on device electrical performance based on a fixed nanowires height and diameter-over-periodicity were investigated under illumination. The variation in quantum efficiency indicated that the performance is limited by the mismatch between light absorption and carriers’ collection length.

Catching the electron in action in real space inside a Ge–Si core–shell nanowire transistor

Nanoscale ◽  
2017 ◽  
Vol 9 (36) ◽  
pp. 13425-13431 ◽  
Author(s):  
Meghnath Jaishi ◽  
Ranjit Pati
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Real Space ◽  
Core Shell ◽  
Nanowire Transistor ◽  
Effect Transistor

Visual manifestation of electronic quantum path in a Ge–Si core–shell nanowire field effect transistor.

Fabrication and characterization of a δ-dope InAs/InP core shell nanowire transistor

2013 ◽  
Vol 378 ◽  
pp. 511-514 ◽  
Author(s):  
Zhixin Cui ◽  
Tomotsugu Ishikura ◽  
Fauzia Jabeen ◽  
J.-C. Harmand ◽  
Kanji Yoh
Keyword(s):  
Core Shell ◽  
Nanowire Transistor ◽  
Fabrication And Characterization

scholarly journals Solid-State Limited Nucleation of NiSi/SiC Core-Shell Nanowires by Hot-Wire Chemical Vapor Deposition

Materials ◽  
2019 ◽  
Vol 12 (4) ◽  
pp. 674 ◽  
Author(s):  
Mahdi Alizadeh ◽  
Najwa binti Hamzan ◽  
Poh Choon Ooi ◽  
Muhammad Firdaus bin Omar ◽  
Chang Fu Dee ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Field Effect Transistors ◽  
Chemical Vapor ◽  
Electrical Performance ◽  
Core Shell ◽  
Hot Wire ◽  
Crystal Silicon ◽  
Surface Migration ◽  
Shell Nanowires

This work demonstrated a growth of well-aligned NiSi/SiC core-shell nanowires by a one-step process of hot-wire chemical vapor deposition on Ni-coated crystal silicon substrates at different thicknesses. The NiSi nanoparticles (60 to 207 nm) acted as nano-templates to initially inducing the growth of these core-shell nanowires. These core-shell nanowires were structured by single crystalline NiSi and amorphous SiC as the cores and shells of the nanowires, respectively. It is proposed that the precipitation of the NiSi/SiC are followed according to the nucleation limited silicide reaction and the surface-migration respectively for these core-shell nanowires. The electrical performance of the grown NiSi/SiC core-shell nanowires was characterized by the conducting AFM and it is found that the measured conductivities of the nanowires were higher than the reported works that might be enhanced by SiC shell layer on NiSi nanowires. The high conductivity of NiSi/SiC core-shell nanowires could potentially improve the electrical performance of the nanowires-based devices for harsh environment applications such as field effect transistors, field emitters, space sensors, and electrochemical devices.

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

A crystalline–amorphous Ni–Ni(OH)2 core–shell catalyst for the alkaline hydrogen evolution reaction

2020 ◽  
Vol 8 (44) ◽  
pp. 23323-23329
Author(s):  
Jing Hu ◽  
Siwei Li ◽  
Yuzhi Li ◽  
Jing Wang ◽  
Yunchen Du ◽  
...  
Keyword(s):  
Hydrogen Evolution ◽  
Hydrogen Evolution Reaction ◽  
Electrocatalytic Activity ◽  
Core Shell ◽  
Alkaline Conditions

Crystalline–amorphous Ni–Ni(OH)2 core–shell assembled nanosheets exhibit outstanding electrocatalytic activity and stability for hydrogen evolution under alkaline conditions.

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