Silicon Nitride Optimisation for A-Si:H Tfts Used in Projection LC-TVS

1994 ◽  
Vol 336 ◽  
Author(s):  
I. D. French ◽  
C. J. Curling ◽  
A.L. Goodyear
Keyword(s):  
Thin Films ◽  
Silicon Nitride ◽  
Electrical Performance ◽  
Storage Capacitor ◽  
Electrical Characteristics ◽  
Large Area ◽  
Step Coverage ◽  
Minimum Number ◽  
Physical Shape ◽  
Nitride Layers

ABSTRACTMulti-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easy to produce individual layers optimised for electrical performance that will physically “pull off’ underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.

Silicon Nitride Optimisation for a-Si:H TFTs Used in Projection LC-TVs

1994 ◽  
Vol 345 ◽  
Author(s):  
I. D. French ◽  
C. J. Curling ◽  
A. L. Goodyear
Keyword(s):  
Thin Films ◽  
Silicon Nitride ◽  
Electrical Performance ◽  
Storage Capacitor ◽  
Electrical Characteristics ◽  
Large Area ◽  
Step Coverage ◽  
Minimum Number ◽  
Physical Shape ◽  
Nitride Layers

AbstractMulti-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easyto produce individual layers optimised for electrical performance that will physically “pull off” underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.

Investigation of Diblock Copolymer thin film Morphology for Nanolithography

1996 ◽  
Vol 461 ◽  
Author(s):  
Miri Park ◽  
Christopher Harrison ◽  
Paul M. Chaikin ◽  
Richard A. Register ◽  
Douglas Adamson ◽  
...  
Keyword(s):  
Thin Films ◽  
Silicon Nitride ◽  
Diblock Copolymer ◽  
Diblock Copolymers ◽  
Microphase Separation ◽  
Large Area ◽  
Etching Technique ◽  
Copolymer Films ◽  
Self Assembled ◽  
Self Assembled Layer

ABSTRACTThe microphase separated morphology of diblock copolymers can be used to generate well-ordered nanometer scale patterns over a large area. To achieve this goal, it is important to understand and control the behavior of diblock copolymer thin films on substrates, which can differ from the bulk behavior. We have investigated the morphologies and ordering in thin polystyrene-polybutadiene (PS-PB) diblock copolymer films on bare silicon and silicon nitride substrates, and also on polymethylmethacrylate (PMMA) coated substrates. The PS-PB copolymers are synthesized to form, in bulk, PB cylinders or spheres in a PS matrix. In thin films (10–60 nm thick), prepared by spin-coating, we observe that the morphology and ordering of the microdomains are affected by strong wetting constraints and a reduced chain mobility on the substrate. The thinnest self-assembled layer of the copolymer films shows no in-plane microphase separation on both types of substrates. The PS blocks wet the PMMA substrates whereas the PB blocks wet the bare substrates as well as the air interface. Hence, different film thicknesses are necessary on the two types of substrates to obtain a uniform film of the first self-assembled cylindrical or spherical microdomain layer. The first layer of the cylindrical copolymer can vary from cylindrical to spherical morphology with a few nanometer decrease in film thickness. In the case of spherical PS-PB diblock copolymer films, we observe that the ordering of the microdomains is improved in the films on the PMMA substrates, compared to those on the bare substrates. We also demonstrate a successful transfer of the microdomain patterns to silicon nitride substrates by a reactive ion etching technique.

Large-Area P-μc-Si:H Thin Films Prepared by VHF-PECVD and its Application in Micromorph Tandem Solar Module

2011 ◽  
Vol 347-353 ◽  
pp. 678-682
Author(s):  
Hui Zhi Ren ◽  
Ying Zhao ◽  
Xiao Dan Zhang ◽  
Hong Ge ◽  
Zong Pan Wang
Keyword(s):  
Thin Films ◽  
Volume Fraction ◽  
Dark Conductivity ◽  
Electrical Characteristics ◽  
Large Area ◽  
Solar Module ◽  
Deposition Parameters ◽  
P Type ◽  
Silane Concentration ◽  
Doping Ratio

Superscript textHigh conductivity,high crystalline volume fraction p-type microcrystaline silicon(p-μc-Si:H) thin films prepared by high-pressure VHF-PECVD are reported in this paper．The effects of the boron concentration, the silane concentration and the plasma power on the microstructures and electrical characteristics of P-μc-Si:H thin films are investigated. The results show that the microstructures and electrical characteristics of thin films relied on the deposition parameters. By optimizing the deposition parameters, very thin(31 nm) P-μc-Si:H thin films have been obtained at the doping ratio of 0.4% , SC at 1.2% and power at 1800W. The Xc of P-μc-Si:H thin films was 67% with 4.3% uniformity ,the dark conductivity was 0.68S/cm with 5.1% uniformity. By employing this P-μc-Si:H thin films, an initial conversion efficiency of 8.12% was obtained for a 0.79 m2a-Si:H/μc-Si:H tandem module by Al as back reflector.

Lattice imaging of Pd2Si thin films

1978 ◽  
Vol 36 (1) ◽  
pp. 304-305
Author(s):  
T.S. Kuan ◽  
K.N. Tu
Keyword(s):  
Thin Films ◽  
High Performance ◽  
Room Temperature ◽  
Ohmic Contacts ◽  
Structural Information ◽  
Electrical Characteristics ◽  
Orientation Relationships ◽  
Lattice Imaging ◽  
Large Area ◽  
Si Films

Thin films of near-noble metal silicide such as Pd2Si and PtSi are now being used as rectifying and ohmic contacts in high performance Si devices. These silicides are made by depositing and annealing the metals on Si. The substrate temperature and orientation and the annealing condition can affect the microstructure of the silicide (1) and in turn change the electrical characteristics of the contact.This study attempts to show that detailed structural information about thin Pd2Si films can be obtained from lattice imaging technique. We chose the Pd2Si because it has a hexogonal structure (2) and grows epitaxially on (111) Si with the orientation relationships:(001)Pd2Si // (111)Si and [100]Pd2Si // [110]Si. The epitaxially-grown film will provide a large area or the single crystal Pd2Si for lattice imaging.The Si wafers used were n-type, 10 to 20 Ω-cm, (111) oriented, and HF etched before deposition. The deposition of Pd film of 100Å was carried out by e-beam evaporation at a rate of ∼5Å/sec. in a vacuum of 2x10-7 torr onto room temperature substrates.

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

scholarly journals Synthesis of N-CNT/TiO2 composites thin films: surface analysis and optoelectronic properties

2020 ◽  
Vol 183 ◽  
pp. 05002 ◽  
Author(s):  
Hamza Belkhanchi ◽  
Younes Ziat ◽  
Maryama Hammi ◽  
Charaf Laghlimi ◽  
Abdelaziz Moutcine ◽  
...  
Keyword(s):  
Thin Films ◽  
Surface Analysis ◽  
Sol Gel ◽  
Careful Analysis ◽  
Optoelectronic Properties ◽  
Spectroscopic Techniques ◽  
Large Area ◽  
Visible Absorption ◽  
Temperature Solution ◽  
Good Agreement

In this study, we have investigated the surface analysis and optoelectronic properties on the synthesis of N-CNT/TiO2 composites thin films, using sol gel method for a dye synthetized solar cell (DSSC) which is found to be simple and economical route. The titanium dioxide based solar cells are an exciting photovoltaic candidate; they are promising for the realization of large area devices. That can be synthetized by room temperature solution processing, with high photoactive performance. In the present work, we stated comparable efficiencies by directing our investigation on obtaining Sol Gel thin films based on N-CNT/TiO2, by dispersing nitrogen (N) doped carbon nanotubes (N-CNTs) powders in titanium tetraisopropoxyde (TTIP). The samples were assessed in terms of optical properties, using UV—visible absorption spectroscopic techniques. After careful analysis of the results, we have concluded that the mentioned route is good and more efficient in terms of optoelectronic properties. The gap of “the neat” 0.00w% N-CNT/TiO2 is of 3eV, which is in a good agreement with similar gap of semiconductors. The incorporated “w%NCNTs” led to diminishing the Eg with increasing N-CNTs amount. These consequences are very encouraging for optoelectronic field.

scholarly journals Strong texture tuning along different crystalline directions in glass-supported CeO2 thin films by ultrasonic spray pyrolysis

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Inti Zumeta-Dubé ◽  
José Manuel García Rangel ◽  
Jorge Roque ◽  
Issis Claudette Romero-Ibarra ◽  
Mario Fidel García Sánchez
Keyword(s):  
Thin Films ◽  
Spray Pyrolysis ◽  
Spray Pyrolysis Technique ◽  
Morphological Characteristics ◽  
Ultrasonic Spray Pyrolysis ◽  
Cost Effective ◽  
Growth Direction ◽  
Large Area ◽  
Smart Windows ◽  
Ultrasonic Spray

AbstractThe strong facet-dependent performance of glass-supported CeO2 thin films in different applications (catalysis, smart windows, etc.) has been the target of diverse fundamental and technological approaches. However, the design of accurate, cost-effective and scalable methods with the potential for large-area coverage that produce highly textured glass-supported CeO2 thin films remains a technological challenge. In the present work, it is demonstrated that under proper tuning conditions, the ultrasonic spray pyrolysis technique enables one to obtain glass-supported polycrystalline CeO2 films with noticeable texture along both the (100) and (111) directions, as well as with randomly oriented crystallites (no texture). The influence of flow rates, solution molarity, and substrate temperature on the texture and morphological characteristics, as well as optical absorption and Raman response of the deposited films, is evaluated. The obtained results are discussed on the basis of the combined dependence of the CeO2-exposed surfaces on the thermodynamic stability of the corresponding facets and the reaction kinetics, which modulate the crystallite growth direction.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

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