scholarly journals Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology

1999 ◽  
Author(s):  
Christopher L. Henderson ◽  
Charles E. Hembree ◽  
Jerry M. Soden ◽  
Thomas J. Headley ◽  
Bruce L. Draper
Keyword(s):  
Power Supply ◽  
Random Access ◽  
Shallow Trench Isolation ◽  
Root Cause ◽  
Trench Isolation ◽  
Static Random Access Memories ◽  
Cause Of Failure ◽  
Radiation Hardened ◽  
Supply Current ◽  
Electrical Analysis

Abstract During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Identifying the Root Cause of Source-Drain Leakage Caused Soft Fail in Advanced Bulk FinFET Devices

2018 ◽  
Author(s):  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chongkhiam Oh
Keyword(s):  
Careful Analysis ◽  
Physical Analysis ◽  
Device Structure ◽  
Tem Analysis ◽  
Root Cause ◽  
3D Architecture ◽  
Cause Of Failure ◽  
Electrical Analysis ◽  
Electrical Data

Abstract The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

A scaleable, radiation hardened shallow trench isolation

1999 ◽  
Vol 46 (6) ◽  
pp. 1836-1840 ◽  
Author(s):  
F.T. Brady ◽  
J.D. Maimon ◽  
M.J. Hurt
Keyword(s):  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Radiation Hardened

STI Punch-through Degradation Related Standby Current Failure in HTOL Test – A Case Study

2007 ◽  
Author(s):  
Wen-Rong Chen ◽  
Wei-Chun Tseng ◽  
Yi-Ju Lee ◽  
Kuang-Wen Liu ◽  
Li-Kuang Kuo ◽  
...  
Keyword(s):  
High Temperature ◽  
Failure Mechanisms ◽  
Circuit Layout ◽  
Shallow Trench Isolation ◽  
Operational Life ◽  
Trench Isolation ◽  
Electrical Analysis ◽  
Stress Experiment

Abstract This report summarizes the analysis results of 0.13µm technology 256Mbits NBit HTOL (High Temperature Operational Life) induced standby current failures caused by STI (Shallow Trench Isolation) punch through induced leakage degradation. Electrical analysis, EMMI and stress experiment on test devices are employed to identify the failure mechanisms, root causes, and corrective solutions. From this study, improvements could be achieved by circuit layout modification.

Dislocation Formation in Trench-Based Dynamic Random Access Memory (DRAM) Chips

1995 ◽  
Vol 405 ◽  
Author(s):  
H. Ho ◽  
E. Hammerl ◽  
R. Stengl ◽  
J. Benedict
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Stress Fields ◽  
Two Dimensional ◽  
Access Memory ◽  
Deep Trench ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Distribution Of Dislocations ◽  
Dislocation Formation

AbstractThis paper reports on our studies of dislocation formation in trench capacitor DRAM structures. Experimental results on process dependence and layout dependence of dislocation formation in cell layouts with minimum feature sizes from 0.5 μm to 0.25 μm are compared to two-dimensional stress simulations. It is shown that the nucleation and spatial distribution of dislocations can be explained by considering stress fields which are influenced by the overlay of deep trench and shallow trench isolation structures.

Easily Manufacturable Shallow Trench Isolation for Gigabit Dynamic Random Access Memory

1996 ◽  
Vol 35 (Part 1, No. 9A) ◽  
pp. 4618-4623 ◽  
Author(s):  
Byung Hyug Roh ◽  
Yun Hee Cho ◽  
Yu Gyun Shin ◽  
Chang Gi Hong ◽  
Sang Dong Gwun ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Shallow Trench Isolation ◽  
Trench Isolation
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