STI Punch-through Degradation Related Standby Current Failure in HTOL Test – A Case Study

Author(s):  
Wen-Rong Chen ◽  
Wei-Chun Tseng ◽  
Yi-Ju Lee ◽  
Kuang-Wen Liu ◽  
Li-Kuang Kuo ◽  
...  

Abstract This report summarizes the analysis results of 0.13µm technology 256Mbits NBit HTOL (High Temperature Operational Life) induced standby current failures caused by STI (Shallow Trench Isolation) punch through induced leakage degradation. Electrical analysis, EMMI and stress experiment on test devices are employed to identify the failure mechanisms, root causes, and corrective solutions. From this study, improvements could be achieved by circuit layout modification.

Author(s):  
Christopher L. Henderson ◽  
Charles E. Hembree ◽  
Jerry M. Soden ◽  
Thomas J. Headley ◽  
Bruce L. Draper

Abstract During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island


Author(s):  
Cha-Ming Shen ◽  
Tsan-Chen Chuang ◽  
Shi-Chen Lin ◽  
Lian-Fon Wen ◽  
Chen-May Huang

Abstract In this paper, we focus on how to identify non-visual failures by way of electrical analysis because some special failures cannot be observed by SEM (scanning electron microscopy) or TEM (transmission electron microscopy) even when they are precisely located by other analytical instrumentation or are symptomatic of an authentic or single suspect. The methodology described here was developed to expand the capabilities of nano-probing via C-AFM (conductive atomic forced microscopy), which can acquire detailed electrical data, and combining the technique with reasoned simulation using various mathematic models emulating all of the significant failure characteristics. Finally, a case study is presented to verify that such defect modes can be identified even when general PFA (physical failure analysis) cannot be implemented for investigating non-visual failure mechanisms.


2012 ◽  
Vol 17 (4) ◽  
pp. 379-384 ◽  
Author(s):  
Krzysztof Strzecha ◽  
Tomasz Koszmider ◽  
Damian Zarębski ◽  
Wojciech Łobodziński

Abstract In this paper, a case-study of the auto-focus algorithm for correcting image distortions caused by gas flow in high-temperature measurements of surface phenomena is presented. This article shows results of proposed algorithm and methods for increasing its accuracy.


Author(s):  
Suk Min Kim ◽  
Jung Ho Lee ◽  
Jong Hak Lee ◽  
Hyung Ki Kim ◽  
Myung Sick Chang ◽  
...  

Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.


1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.


Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.


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