Study on a Single NFET Degradation After Circuit Modification With FIB

Author(s):  
Werner Lehner

Abstract The use of FIB in circuit modification can generate huge influences on MOS transistor parameters. It is necessary to investigate and understand the effects that occur after Ga irradiation to evaluate the influence on the behaviour of the modified structures. In this paper we investigate influences on the threshold voltage of an n-FET MOS transistor in a standard, state of the art 0.17 µm DRAM technology, after FIB irradiation. In particular, the effect of varying the distance (vertical and horizontal) between the location of the FIB modification and the active area as well as the possibility of recovering the induced Vth shift has been characterized.

2008 ◽  
Vol 600-603 ◽  
pp. 895-900 ◽  
Author(s):  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Robert Callanan ◽  
Craig Capell ◽  
Mrinal K. Das ◽  
...  

In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.


2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.


Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2118
Author(s):  
Gwang Hui Choi ◽  
Taehui Na

Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in the reduction of battery lifetime. The most effective method to extend the battery lifetime is to shut-off the device during standby mode. For this reason, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ) based nonvolatile flip-flop (NVFF) is being considered as a strong candidate to store the computing data. Since there is a risk that the MTJ resistance may change during the read operation (i.e., the read disturbance problem), NVFF should consider the read disturbance problem to satisfy reliable data restoration. To date, several NVFFs have been proposed. Even though they satisfy the target restore yield of 4σ, most of them do not take the read disturbance into account. Furthermore, several recently proposed NVFFs which focus on the offset-cancellation technique to improve the restore yield have obvious limitation with decreasing the supply voltage (VDD), because the offset-cancellation technique uses switch operation in the critical path that can exacerbate the restore yield in the near/sub-threshold region. In this regard, this paper analyzes state-of-the-art STT-MTJ based NVFFs with respect to the voltage region and provides insight that a simple circuit having no offset-cancellation technique could achieve a better restore yield in the near/sub-threshold voltage region. Monte–Carlo HSPICE simulation results, using industry-compatible 28 nm model parameters, show that in case of VDD of 0.6 V, complex NVFF circuits having offset tolerance characteristic have a better restore yield, whereas in case of VDD of 0.4 V with sizing up strategy, a simple NVFF circuit having no offset tolerance characteristic has a better restore yield.


2017 ◽  
Vol 23 (2) ◽  
pp. 247-254 ◽  
Author(s):  
Nicolas Rolland ◽  
François Vurpillot ◽  
Sébastien Duguay ◽  
Baishakhi Mazumder ◽  
James S. Speck ◽  
...  

AbstractAccuracy of atom probe tomography measurements is strongly degraded by the presence of phases that have different evaporation fields. In particular, when there are perpendicular interfaces to the tip axis in the specimen, layers thicknesses are systematically biased and the resolution is degraded near the interfaces. Based on an analytical model of field evaporated emitter end-form, a new algorithm dedicated to the 3D reconstruction of multilayered samples was developed. Simulations of field evaporation of bilayer were performed to evaluate the effectiveness of the new algorithm. Compared to the standard state-of-the-art reconstruction methods, the present approach provides much more accurate analyzed volume, and the resolution is clearly improved near the interface. The ability of the algorithm to handle experimental data was also demonstrated. It is shown that the standard algorithm applied to the same data can commit an error on the layers thicknesses up to a factor 2. This new method is not constrained by the classical hemispherical specimen shape assumption.


2003 ◽  
Vol 50 (11) ◽  
pp. 2297-2300 ◽  
Author(s):  
Shengdong Zhang ◽  
Xinnan Lin ◽  
Ru Huang ◽  
Ruqi Han ◽  
Mansun Chan

2021 ◽  
Vol 8 ◽  
Author(s):  
Phillip Quin ◽  
Dac Dang Khoa Nguyen ◽  
Thanh Long Vu ◽  
Alen Alempijevic ◽  
Gavin Paul

Many robot exploration algorithms that are used to explore office, home, or outdoor environments, rely on the concept of frontier cells. Frontier cells define the border between known and unknown space. Frontier-based exploration is the process of repeatedly detecting frontiers and moving towards them, until there are no more frontiers and therefore no more unknown regions. The faster frontier cells can be detected, the more efficient exploration becomes. This paper proposes several algorithms for detecting frontiers. The first is called Naïve Active Area (NaïveAA) frontier detection and achieves frontier detection in constant time by only evaluating the cells in the active area defined by scans taken. The second algorithm is called Expanding-Wavefront Frontier Detection (EWFD) and uses frontiers from the previous timestep as a starting point for searching for frontiers in newly discovered space. The third approach is called Frontier-Tracing Frontier Detection (FTFD) and also uses the frontiers from the previous timestep as well as the endpoints of the scan, to determine the frontiers at the current timestep. Algorithms are compared to state-of-the-art algorithms such as Naïve, WFD, and WFD-INC. NaïveAA is shown to operate in constant time and therefore is suitable as a basic benchmark for frontier detection algorithms. EWFD and FTFD are found to be significantly faster than other algorithms.


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