Functional Failure Analysis by Induced Stimulus

2002 ◽  
Author(s):  
Jim Colvin
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Deep Submicron ◽  
Thermal Gradients ◽  
Small Signal ◽  
Fault Testing ◽  
Analysis Techniques ◽  
Leakage Path ◽  
Design Deficiencies ◽  
External Stimuli

Abstract In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or e-beam to induce a parametric shift which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. RIL (Resistive Interconnect Localization) is a newer technique which can identify via anomalies functionally using induced thermal gradients to the metal but does not address how to uniformly inject the thermal energy required in the silicon to analyze timing design deficiencies and other defects.[1] With SIFT (Stimulus Induced Fault Testing), numerous stimuli will be used to identify speed, fault, and parametric differences in silicon. The heart of this technique revolves around intentionally disturbing devices with external stimuli and comparing the test criteria to reference parts or timing/voltage sensitivities. Synchronous interfacing is possible to any tester without any wiring or program changes.

Gradient Thermal Analysis by Induced Stimulus

2009 ◽  
Author(s):  
Jim Colvin
Keyword(s):  
Integrated Circuits ◽  
Deep Submicron ◽  
Temperature Sensitive ◽  
Thermal Gradients ◽  
Small Signal ◽  
3 Dimensional ◽  
Analysis Techniques ◽  
Dc Power ◽  
Leakage Path ◽  
Measured Response

Abstract In the field of failure analysis of integrated circuits, diagnosing functional failures is a requirement. Traditional beam-based analysis techniques use a scanning laser or ebeam to induce a parametric shift, which is monitored through changes in current or voltage driven to the device. Deep submicron technologies frustrate these analytical methods due to the nearly immeasurable parametric shifts externally caused by a small signal leakage path internally. These internal failures can be identified functionally by timing, temperature or voltage dependencies but the exact location of the fault is difficult to isolate. SIFT (Stimulus Induced Fault Test), RIL (Resistive Interconnect Localization) and SDL (Soft Defect Localization) can identify anomalies functionally using induced thermal gradients to the metal but does not address how to analyze embedded temperature sensitive defects inaccessible to the laser. 1,2,3,4 Stacked die and similar 3 dimensional (3D) devices complicate the analysis requiring destruction/removal of one or more die. This paper will show how to create quantifiable thermal gradients to a defect and triangulate the location of the defect in 1, 2, and 3 dimensions as follows: 1. Apply a differential temperature gradient across the device in each of the X,Y, and Z-axes. The defect is localized based on its measured response in the gradient as the gradient sweeps across. 2. Induce a gradient with a laser and use the measurement of DC power required to relate the distance to the defect from various locations in relation to a heat sink. 3. Measure the time of flight of the thermal propagation to a defect from known laser positions to triangulate the location of the defect.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

2016 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista ◽  
Ulrike Kindereit
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Electron Hole ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
Electron Hole Pair ◽  
Pair Generation ◽  
Silicon Thickness ◽  
Performance Timing ◽  
Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

New Rapid Failure Analysis Techniques for Multilevel Metallization

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 74-77
Author(s):  
Edward I. Cole ◽  
Richard E. Anderson
Keyword(s):  
Integrated Circuits ◽  
Product Development ◽  
Failure Analysis ◽  
New Product Development ◽  
New Product ◽  
Electronics Industry ◽  
New Techniques ◽  
Analysis Techniques ◽  
Advantages And Disadvantages ◽  
Failure Site

Open interconnections on integrated circuits (ICs) are a serious and ubiquitous problem throughout the micro-electronics industry. The efforts to understand the mechanisms responsible for producing open interconnections and to develop analytical methods to localize them demonstrate the concern manufacturers have for this problem. Multiple layers of metallization not only increase the probability that an open conductor or via will occur because of the increased number of interconnections and vias but also increase the difficulty in localizing the site of the failure because upper layers may mask the failure site.Rapid failure analysis of open-conductor defects is critical in new product development and reliability assessment of ICs where manufacturing and product development delays can cost millions of dollars a day. In this article, we briefly review some standard failure analysis approaches and then concentrate on new techniques to rapidly locate open-conductor defects that would have been difficult or impossible to identify using earlier methods. Each method is described in terms of the physics of signal generation, application, and advantages and disadvantages when compared to existing methods.

Optical Failure Analysis Technique in Deep Submicron CMOS Integrated Circuits

2011 ◽  
Vol 11 (4) ◽  
pp. 302-308
Author(s):  
Sunk-Won Kim ◽  
Hyong-Min Lee ◽  
Hyun-Joong Lee ◽  
Jong-Kwan Woo ◽  
Jun-Ho Cheon ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Deep Submicron ◽  
Cmos Integrated Circuits ◽  
Analysis Technique ◽  
Submicron Cmos

A Study of Effects of Backside Thinning on Integrated Circuits Using a Precision Diamond Wheel Apparatus

1998 ◽  
Author(s):  
S.P. Roberts ◽  
J.M. Patterson
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Diamond Wheel ◽  
Packaging Material ◽  
Analysis Techniques ◽  
Recent Advances ◽  
Specialized Equipment

Abstract Recent advances in integrated circuit technologies and in interconnect methodologies to external electronics have made it extremely difficult to conduct failure analysis from the top side of the die (1,2). Therefore analysis techniques are being developed that allow analysis from the backside of the die. The first step in this process involves gaining access to the back of the die through the packaging material. Most backside analysis techniques require that the die then be thinned and polished. This paper describes specialized equipment and procedures to meet those requirements. The equipment is relatively inexpensive compared to other approaches.

Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-Thin Remaining Thickness

2015 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
End Of Life ◽  
Surface Damage ◽  
Active Device ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
One Step ◽  
Silicon Thickness ◽  
Test Package

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.

Ultra-Thinning of Silicon for Backside Fault Isolation

2019 ◽  
Author(s):  
M. J. Campin ◽  
P. Nowakowski ◽  
P. E. Fischione
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
State Of The Art ◽  
Fault Isolation ◽  
Infrared Light ◽  
Ion Milling ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Broad Beam ◽  
Silicon Thickness

Abstract The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

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