Ultra-Thinning of Silicon for Backside Fault Isolation

2019 ◽  
Author(s):  
M. J. Campin ◽  
P. Nowakowski ◽  
P. E. Fischione
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
State Of The Art ◽  
Fault Isolation ◽  
Infrared Light ◽  
Ion Milling ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Broad Beam ◽  
Silicon Thickness

Abstract The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

2016 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista ◽  
Ulrike Kindereit
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Electron Hole ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
Electron Hole Pair ◽  
Pair Generation ◽  
Silicon Thickness ◽  
Performance Timing ◽  
Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

Targeted Silicon Ultra-Thinning by Contour Milling for Advanced Fault Isolation

2019 ◽  
Author(s):  
W. S. Teo ◽  
M.S. Wei ◽  
V. Narang ◽  
C. L. Gan ◽  
C. Richardson ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Thin Sample ◽  
Electrical Failure ◽  
Contour Maps ◽  
Area Of Interest ◽  
Silicon Thickness ◽  
Thermal Stability Of

Abstract In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

Adaptive Grinding and Polishing of Silicon Integrated Circuits to Ultra-Thin Remaining Thickness

2015 ◽  
Author(s):  
Robert Chivas ◽  
Scott Silverman ◽  
Michael DiBattista
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
End Of Life ◽  
Surface Damage ◽  
Active Device ◽  
Analysis Techniques ◽  
Silicon Integrated Circuits ◽  
One Step ◽  
Silicon Thickness ◽  
Test Package

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.

Detection and Characterization of an Electrical Failure Induced during Laser Ablation of Packages

2008 ◽  
Author(s):  
P. Schwindenhammer ◽  
H. Murray ◽  
P. Descamps ◽  
P. Poirier
Keyword(s):  
Laser Ablation ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Ablation Process ◽  
Thermally Induced ◽  
Electrical Failure ◽  
Electrical Phenomenon ◽  
Semiconductor Packages ◽  
Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

The Influence of Optical Beams on Semiconductor Devices During Failure Analysis

2002 ◽  
Author(s):  
Charles Zhang ◽  
Matt Thayer ◽  
Lowell Herlinger ◽  
Greg Dabney ◽  
Manuel Gonzalez
Keyword(s):  
Failure Analysis ◽  
Semiconductor Devices ◽  
Laser Wavelength ◽  
Fault Isolation ◽  
Analysis Techniques ◽  
Cmos Transistor ◽  
Optical Beams

Abstract A number of backside analysis techniques rely on the successful use of optical beams in performing backside fault isolation. In this paper, the authors have investigated the influence of the 1340 nm and 1064 nm laser wavelength on advanced CMOS transistor performance.

New Rapid Failure Analysis Techniques for Multilevel Metallization

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 74-77
Author(s):  
Edward I. Cole ◽  
Richard E. Anderson
Keyword(s):  
Integrated Circuits ◽  
Product Development ◽  
Failure Analysis ◽  
New Product Development ◽  
New Product ◽  
Electronics Industry ◽  
New Techniques ◽  
Analysis Techniques ◽  
Advantages And Disadvantages ◽  
Failure Site

Open interconnections on integrated circuits (ICs) are a serious and ubiquitous problem throughout the micro-electronics industry. The efforts to understand the mechanisms responsible for producing open interconnections and to develop analytical methods to localize them demonstrate the concern manufacturers have for this problem. Multiple layers of metallization not only increase the probability that an open conductor or via will occur because of the increased number of interconnections and vias but also increase the difficulty in localizing the site of the failure because upper layers may mask the failure site.Rapid failure analysis of open-conductor defects is critical in new product development and reliability assessment of ICs where manufacturing and product development delays can cost millions of dollars a day. In this article, we briefly review some standard failure analysis approaches and then concentrate on new techniques to rapidly locate open-conductor defects that would have been difficult or impossible to identify using earlier methods. Each method is described in terms of the physics of signal generation, application, and advantages and disadvantages when compared to existing methods.

Fault Isolation of Large Nets Using Bridging Fault Analysis

2004 ◽  
Author(s):  
George Ontko
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Analysis ◽  
Fault Isolation ◽  
Bridging Faults ◽  
Bridging Fault

Abstract Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.

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