Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Failure Analysis of SRAM DQ Fault Using BIST Pattern

2018 ◽  
Author(s):  
KeonIl Kim ◽  
Yoseop Lim ◽  
GhilGeun Oh ◽  
ShinYoung Chung ◽  
Brandon Lee
Keyword(s):  
Failure Analysis ◽  
Process Improvement ◽  
Fault Location ◽  
Fault Isolation ◽  
Experimental Results ◽  
Yield Enhancement ◽  
Input Output ◽  
Isolation Technique ◽  
Innovative Method ◽  
Self Test

Abstract SRAM failure analysis (FA) provides significant value to process improvement and yield enhancement. This paper introduces an innovative method to analyze the SRAM peripheral, particularly its input/output (DQ) failures, which is not easy to isolate the fault location. In this paper, SRAM Built-In Self-Test (BIST) logic is used to generate the vectors to toggle only DQ of SRAM and an optical fault isolation technique applies to isolate the fault location. Experimental results show that the proposed method is very effective to isolate timing fault and hard defect of SRAM DQ failures.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Analog and Mixed Signal Diagnosis Flow Using Fault Isolation Techniques and Simulation

2020 ◽  
Author(s):  
Tommaso Melis ◽  
Emmanuel Simeu ◽  
Etienne Auvray
Keyword(s):  
Failure Analysis ◽  
Fault Simulation ◽  
Fault Isolation ◽  
Physical Analysis ◽  
Actual Process ◽  
Electrical Test ◽  
Simulation Tools ◽  
Isolation Techniques ◽  
Process Node ◽  
Emission Microscopy

Abstract Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

Improving Fault Isolation Using Iterative Diagnosis

2008 ◽  
Author(s):  
Kevin Gearhardt ◽  
Chris Schuermyer ◽  
Ruifeng Guo
Keyword(s):  
Fault Diagnosis ◽  
Failure Analysis ◽  
Test Generation ◽  
Pattern Generation ◽  
Fault Isolation ◽  
Isolation Techniques ◽  
Defect Localization

Abstract This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysts to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.

Verification of DLS Data by LVP in Case of Marginal Failure

2016 ◽  
Author(s):  
Keonil Kim ◽  
Sungjin Kim ◽  
Kunjae Lee ◽  
Kyeongju Jin ◽  
Yunwoo Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Location ◽  
Photon Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
The Real ◽  
Defect Isolation ◽  
The Relationship ◽  
Non Destructive

Abstract In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement

2004 ◽  
Author(s):  
Chia Ling Kong ◽  
Mohammed R. Islam
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Low Voltage ◽  
Circuit Simulation ◽  
Physical Structure ◽  
Fault Isolation ◽  
Embedded Memory ◽  
Yield Improvement ◽  
Multi Level

Abstract Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Efficient Fault Isolation and Failure Analysis Methods to Root Cause Defects in Microprocessors

2019 ◽  
Author(s):  
Hasan Faraby ◽  
Tristan Deborde ◽  
Martin von Haartman
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
State Of The Art ◽  
Fault Isolation ◽  
High Success Rate ◽  
Electrical Isolation ◽  
Root Cause ◽  
Isolation Techniques ◽  
Analysis Methods

Abstract This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

ATPG Testing and Diagnosis Implementation in Failure Analysis for a Fast and Efficient Iterative ATPG Diagnosis and Fault Isolation

2017 ◽  
Author(s):  
Eric Barbian ◽  
Rommel Estores
Keyword(s):  
Failure Analysis ◽  
Dynamic Analysis ◽  
Creative Thinking ◽  
Complex Analysis ◽  
Cost Effective ◽  
Fault Isolation ◽  
Practical Implementation ◽  
Root Cause ◽  
Isolation Techniques ◽  
Thinking Process

Abstract This paper will present a practical implementation of ATPG testing and diagnosis in Failure Analysis resulting in a fast and efficient iterative ATPG diagnosis and fault isolation. On this implementation, a compact test HW instead of an ATE is used for cost-effective ATPG testing and characterization capability. The advantages of this implementation are combined with ATPG tools to make it possible to achieve a faster and more efficient implementation of iterative ATPG diagnosis, Dynamic Analysis by Laser Stimulation (DALS) analysis or similar techniques. The requirements needed in order to implement ATPG testing and diagnosis in FA lab will be discussed. Success in determining root cause, especially on the complex analysis cases is determined by the complimentary combination of various fault isolation techniques. Knowledge of the fundamentals of these techniques combined with creative thinking process of the analyst leads to the approaches and solutions that maximize the combined advantages of these techniques.

Fault Isolation Techniques and Studies on Low Resistance Gross Short Failures

2012 ◽  
Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
W.Y. Lee ◽  
Y.Z. Ma ◽  
R. He ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Semiconductor Devices ◽  
Fault Isolation ◽  
Nanoscale Devices ◽  
Nanometer Range ◽  
Low Resistance ◽  
Isolation Techniques ◽  
Different Types ◽  
Scaling Down

Abstract With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

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