System Failure Analysis Process and Case Study

2006 ◽  
Author(s):  
Nicholas Konkol
Keyword(s):  
Failure Analysis ◽  
Personal Computer ◽  
Failure Mechanisms ◽  
System Level ◽  
System Failure ◽  
Quality Improvements ◽  
Analysis Process ◽  
Electrical Overstress ◽  
Type Of Failure

Abstract Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.

Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator

2017 ◽  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan
Keyword(s):  
Heat Source ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
System Level ◽  
Thermal Failure ◽  
Analysis Process ◽  
Lock In

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Using a Unified Data Stream to Drive Failure Analysis for Product Improvement in the Personal Computer (PC) Environment

2006 ◽  
Author(s):  
Shirleen Horley ◽  
Joseph Rascon
Keyword(s):  
Failure Analysis ◽  
Personal Computer ◽  
Data Stream ◽  
Root Cause ◽  
Analysis Process ◽  
Development Teams ◽  
Wide Range ◽  
Product Manufacturing ◽  
Value Add ◽  
Analysis System

Abstract The longer defective units are in the manufacturing pipeline before they are detected, the more expensive it becomes. Economic pressures drive the requirement to capture failures and perform root cause analysis further upstream in the product manufacturing cycle. This places greater emphasis on the ability to identify failures and perform value add analysis to drive product improvements as early as possible. This paper describes the method used to develop a reliable Unified Data Stream (UDS) that feeds the failure analysis process which in turn provides actionable information to product development teams in the Personal Computer (PC) environment. This manuscript describes the development and implementation of the Unified Data Stream designed to replace ambiguity and uncertainty with a defect trend and symptom pareto that drives action upstream. Focus will be on the output of UDS enabling the prioritization of product defects that feed the failure analysis system. Additionally, this paper will touch on the application of the UDS system for different types of pc components. The future of UDS is without bounds as it can also be applied to a wide range of products.

Flip-Chip Bump Interface Failure Mechanisms In Plastic BGA Packages and Failure Analysis Process Flow

2008 ◽  
Author(s):  
Zhaofeng Wang
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Integrity Test ◽  
Forming Process ◽  
Interface Failure ◽  
Process Flow ◽  
Analysis Process ◽  
Bga Packages ◽  
Intermittent Contact

Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

A Failure Analysis Method Based on the Combination of FTA and GGRA: A Case Study on an Engine

2021 ◽  
Vol 53 ◽  
pp. 53-66
Author(s):  
Jun Li Shi ◽  
Huai Zhi Wang ◽  
Jun Yu Hu ◽  
Yun Dong Ma ◽  
Ming Yang Ma ◽  
...  
Keyword(s):  
Failure Analysis ◽  
System Failure ◽  
Analysis Method ◽  
Product System ◽  
Grey Relation Analysis ◽  
Complex Product ◽  
Relation Analysis ◽  
Fault Mode ◽  
Grey Relation

As product structure becomes more and more complex, the fault mode presents a diversified trend, and it is more difficult to determine the causes of system failure for a complex product. The main objective of this study is to provide an effective failure analysis method based on the combination of fault trees analysis (FTA) and generalized grey relation analysis (GGRA) for complex product. In this method, the product system failure is defined and the fault tree is constructed by FTA methodology firstly; and then GGRA is employed to identify the correlations between each fault mode and the system failure; finally, the main causes of system failure are identified and the corresponding measures can be made. A case study of a WD615 Steyr engine is conducted throughout the text to verify the validity of this method. The present study would help facilitate the failure and reliability analysis for complex product and benefit designers for the product improvement.

Fluorosilicate Glass (FSG) Outgassing Induced Aluminum Bond Pad Corrosion during Post-Fab Wafer Storage

2012 ◽  
Author(s):  
Hua Younan ◽  
Nistala Ramesh Rao ◽  
Chen Shuting
Keyword(s):  
Failure Analysis ◽  
Failure Mode ◽  
Subsequent Removal ◽  
Left Behind ◽  
Gas Chemistry ◽  
Type Of Failure

Abstract A case study of Fluorine (F)-outgassing is presented in this paper that caused the corrosion of Aluminum bond pad. It will be shown that the source of F-contamination is not the typical residue left behind after the passivation etch with Fluorine-based gas chemistry and the subsequent removal of the etch polymer generated with solvent (chemical) clean. Rather, it is introduced as a result of F-outgas over a period of time from the intermetallic dielectric (IMD) film, fluorosilicate glass (FSG), during the post-fab wafer storage. The methodology used in our failure analysis (FA) lab to identify and characterize this type of failure mode is presented in the paper.

Anamnesis in Failure Analysis—How a System-Related Approach Can Save Failure Analysis (FA) Time, Shorten Learning Loops and Reduce Cost

2013 ◽  
Author(s):  
Peter Jacob
Keyword(s):  
Failure Analysis ◽  
System Level ◽  
Illustrative Case ◽  
Medical Sciences ◽  
Device Failure ◽  
Root Cause ◽  
Related Approach ◽  
Illustrative Case Study ◽  
The Right

Abstract Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis

2008 ◽  
Author(s):  
K. Li ◽  
P. Liu ◽  
J. Teong ◽  
M. Lee ◽  
H. L. Yap
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
High Resistance ◽  
Cause Analysis ◽  
Logical Problem ◽  
Root Cause ◽  
Analysis Process ◽  
Problem Solving Process

Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device

2000 ◽  
Author(s):  
Steve Hsiung ◽  
Victer Chan
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Fault Identification ◽  
Process Flow ◽  
Packaging Technology ◽  
Root Cause ◽  
Analysis Process ◽  
Complex Construction ◽  
Non Destructive

Abstract With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

EOS (Electrical Overstress) – The Old, Unknown Phenomenon?

2012 ◽  
Author(s):  
Peter Jacob
Keyword(s):  
Electrostatic Discharge ◽  
Failure Mechanisms ◽  
System Level ◽  
Device Failure ◽  
Electrical Overstress ◽  
Dominant Root

Abstract Frequently, Electrical Overstress (EOS) is understood in a similar context like Electrostatic Discharge (ESD). However, when looking deeper, only 3-5% of EOS failure signatures are caused by ESD. The dominant root causes can be found on system level – often inaccessible for the device failure analyst. However, switching procedures and sometimes-hidden inductance loads are the unconsidered and undiscovered problem makers. This paper reviews and highlights these failure mechanisms.

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