Using a Unified Data Stream to Drive Failure Analysis for Product Improvement in the Personal Computer (PC) Environment

2006 ◽  
Author(s):  
Shirleen Horley ◽  
Joseph Rascon
Keyword(s):  
Failure Analysis ◽  
Personal Computer ◽  
Data Stream ◽  
Root Cause ◽  
Analysis Process ◽  
Development Teams ◽  
Wide Range ◽  
Product Manufacturing ◽  
Value Add ◽  
Analysis System

Abstract The longer defective units are in the manufacturing pipeline before they are detected, the more expensive it becomes. Economic pressures drive the requirement to capture failures and perform root cause analysis further upstream in the product manufacturing cycle. This places greater emphasis on the ability to identify failures and perform value add analysis to drive product improvements as early as possible. This paper describes the method used to develop a reliable Unified Data Stream (UDS) that feeds the failure analysis process which in turn provides actionable information to product development teams in the Personal Computer (PC) environment. This manuscript describes the development and implementation of the Unified Data Stream designed to replace ambiguity and uncertainty with a defect trend and symptom pareto that drives action upstream. Focus will be on the output of UDS enabling the prioritization of product defects that feed the failure analysis system. Additionally, this paper will touch on the application of the UDS system for different types of pc components. The future of UDS is without bounds as it can also be applied to a wide range of products.

Leveraging Root Cause Deconvolution Analysis for Logic Yield Ramping

2013 ◽  
Author(s):  
Yan Pan ◽  
Atul Chittora ◽  
Kannan Sekar ◽  
Goh Szu Huat ◽  
You Guo Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Comprehensive Analysis ◽  
Paper Briefly ◽  
Yield Improvement ◽  
Deconvolution Analysis ◽  
Analysis Techniques ◽  
Root Cause ◽  
Conventional Analysis ◽  
Analysis System ◽  
Over Time

Abstract The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.

Defect Isolation Tools Accelerate the Failure Analysis Process

2013 ◽  
Author(s):  
Adam Winterstrom ◽  
Kevin Meehan ◽  
Ralph Sanchez ◽  
Rich Ackerman
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Lead Time ◽  
Functional Test ◽  
Diagnostic Process ◽  
Successful Completion ◽  
Root Cause ◽  
Analysis Process ◽  
Scan Test ◽  
Defect Isolation

Abstract This paper presents case studies that highlight the use of novel scan technologies and techniques to quickly test, diagnose, localize, and isolate the root cause of the defects, demonstrating that the solution meets the rapid and constant changing demands of industry. Cases include a device that has seemingly passed the functional test, but not the scan test with emission; a device with emission requiring resolution to its location; and a device having a timing issue that does not have emission. All case studies concluded with successful completion of finding the root cause of the defect. The diagnosis time for each of the three devices was within a period of one to three days per device. The confirmation stage of the defect is the longest lead time of the diagnostic process.

Words for the “Whys”

2012 ◽  
Author(s):  
Richard J. Ross
Keyword(s):  
Human Brain ◽  
Failure Analysis ◽  
State Of The Art ◽  
Intellectual Curiosity ◽  
Basic Tool ◽  
Cause Analysis ◽  
Root Cause ◽  
Analysis Process ◽  
Tools And Techniques ◽  
Attention To Detail

Abstract In an era where the complexity and cost of Failure Analysis tools and techniques is rapidly expanding, it is easy sometimes to lose sight of the basic tool and technique required for successful root-cause analysis. That technique is intellectual curiosity and the tool is the human brain. This paper will describe a simple methodology to insure that this tool and technique are properly engaged either concomitant with or in the absence of state-of-the-art instrumentation and computation. Two simple case studies will be used to illustrate where the Failure Analysis process can easily go awry without proper attention to detail, and, conversely, from too much attention to detail.

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis

2008 ◽  
Author(s):  
K. Li ◽  
P. Liu ◽  
J. Teong ◽  
M. Lee ◽  
H. L. Yap
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
High Resistance ◽  
Cause Analysis ◽  
Logical Problem ◽  
Root Cause ◽  
Analysis Process ◽  
Problem Solving Process

Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

Failure Analysis Process Flows and Common Failure Mechanisms in Flip-Chip Packaged Device

2000 ◽  
Author(s):  
Steve Hsiung ◽  
Victer Chan
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Failure Mechanisms ◽  
Fault Identification ◽  
Process Flow ◽  
Packaging Technology ◽  
Root Cause ◽  
Analysis Process ◽  
Complex Construction ◽  
Non Destructive

Abstract With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

Failure Analysis Methodology on Circular Patch Functional Failure Due to Device Parametric Drift

2015 ◽  
Author(s):  
A.C.T. Quah ◽  
C.Q. Chen ◽  
G.B Ang ◽  
D. Nagalingam ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Deep Dive ◽  
Circular Patch ◽  
Root Cause ◽  
Analysis Methodology ◽  
Analysis Process ◽  
Value Add ◽  
Challenging Situation ◽  
Leakage Failure ◽  
Parametric Drift

Abstract This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

System Failure Analysis Process and Case Study

2006 ◽  
Author(s):  
Nicholas Konkol
Keyword(s):  
Failure Analysis ◽  
Personal Computer ◽  
Failure Mechanisms ◽  
System Level ◽  
System Failure ◽  
Quality Improvements ◽  
Analysis Process ◽  
Electrical Overstress ◽  
Type Of Failure

Abstract Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.

Vdd Leakage Analysis by a Combination of Various Failure Analysis Techniques

2008 ◽  
Author(s):  
Z. G. Song ◽  
S. B. Ippolito ◽  
P. J. McGinnis ◽  
A. Shore ◽  
B. Paulucci ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Hot Spot ◽  
Fault Isolation ◽  
Physical Analysis ◽  
Analysis Techniques ◽  
Root Cause ◽  
Defect Location ◽  
Analysis Methodology ◽  
Analysis Process ◽  
Leakage Failure

Abstract It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

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