Use of Lock-In Thermography for Non-Destructive 3D Defect Localization on System in Package and Stacked-Die Technology

Author(s):  
Rudolf Schlangen ◽  
Shinobu Motegi ◽  
Toshi Nagatomo ◽  
Christian Schmidt ◽  
Frank Altmann ◽  
...  

Abstract With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.

Author(s):  
Falk Naumann ◽  
Frank Altmann ◽  
Christian Grosse ◽  
Rolf Herold

Abstract Lock-in Thermography in combination with spectral phase shift analysis provides a capability for non-destructive 3D localization of resistive defects in packaged and multi stacked die devices. In this paper a novel post processing approach will be presented allowing a significant reduction of measurement time by factor >5 in comparison to the standard measurement routine. The feasibility of the approach is demonstrated on a specific test specimen made from ideal homogenous and opaque material and furthermore on a packaged hall sensor device. Within the case studies the results of multiple single LIT measurements were compared with the new multi harmonics data analysis approach.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002160-002198
Author(s):  
Rudolf Schlangen ◽  
Herve Deslandes ◽  
Toru Toda ◽  
Toshinobu Nagatomo ◽  
Shigeki Sako ◽  
...  

Root cause analysis for package defects is currently performed by de-processing the package until such defects can be physically seen. However, many such defects within the package are removed, or are confused with defects created during de-processing itself. 3D X-ray has been used to analyze such physical defects within a packaged device in a non-destructive manner. However, the increasing density and associated shrinkage of components such as multi-layered substrates require significantly higher resolutions, which translates to longer times. High resolution X-ray is impractical when searching for a defect over a wide area due to the time to acquire detailed 3D images (~24 hrs). Thermal emission analysis has been widely used for localizing defects on ICs. Recent advancement in thermal emission camera technology coupled with lock-in thermography has allowed orders of magnitude better sensitivity ( < 1μW) and improvement in localization resolution (x,y to < 3 um). However, the application of lock-in thermography has been primarily limited to defect localization at the die level [1]. A a highly sensitive MWIR camera combined with a real time lock-in technique demonstrates the capability to localize defects within packaged devices, even through its mold compound. The technique accurately predicts the depth (z) of a thermal defect within the device (< + 5%) This paper will demonstrate multiple examples of the successful combination of advanced lock-in thermography analysis and high resolution 3D X-ray for totally non-destructive defect location within a packaged device. This initial accurate thermal localization in x, y and z enables the high resolution 3D X-ray system to focus analysis to a few microns so that the defect can be seen quickly (< 1 hr), enabling detection and analysis of previously undetected defects with highest throughput.


Author(s):  
B. Zee ◽  
W. Qiu ◽  
J. Alton ◽  
T. White ◽  
M. Igarashi ◽  
...  

Abstract We demonstrate how electro optical terahertz pulse reflectometry (EOTPR) can be used in conjunction with a new one-dimensional lump circuit simulation software to quickly and non-destructively isolate faults in advanced IC packages. In the case studies presented, short failures are accurately located in a series of advanced IC package.


Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Ingrid de Wolf ◽  
Sebastian Brand

Abstract Tremendous research efforts have been devoted particularly to the development and improvement of through silicon vias (TSV) in order to provide a key enabling technology for vertical system integration. To achieve high processing yield and reliability efficient failure analysis techniques for process control and root cause analysis are required. The current paper presents an advanced approach for non-destructive localization of TSV sidewall defects applying high resolution Lock-in Thermography and Photoemission Microscopy imaging and defocusing series.


Author(s):  
A.C.T. Quah ◽  
S.H. Goh ◽  
V.K. Ravikumar ◽  
S.L. Phoa ◽  
V. Narang ◽  
...  

Abstract The spatial resolution and sensitivity of laser induced techniques are significantly enhanced by combining refractive solid immersion lens technology and laser pulsing with lock-in detection algorithm. Laser pulsing and lock-in detection enhances the detection sensitivity and removes the ‘tail’ artifacts due to amplifier ac-coupling response. Three case studies on microprocessor devices with different failure modes are presented to show that the enhancements made a difference between successful and unsuccessful defect localization.


2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.


Author(s):  
O. Breitenstein ◽  
J.P. Rakotoniaina ◽  
F. Altmann ◽  
J. Schulz ◽  
G. Linse

Abstract In this paper new thermographic techniques with significant improved temperature and/or spatial resolution are presented and compared with existing techniques. In infrared (IR) lock-in thermography heat sources in an electronic device are periodically activated electrically, and the surface is imaged by a free-running IR camera. By computer processing and averaging the images over a certain acquisition time, a surface temperature modulation below 100 µK can be resolved. Moreover, the effective spatial resolution is considerably improved compared to stead-state thermal imaging techniques, since the lateral heat diffusion is suppressed in this a.c. technique. However, a serious limitation is that the spatial resolution is limited to about 5 microns due to the IR wavelength range of 3 -5 µm used by the IR camera. Nevertheless, we demonstrate that lock-in thermography reliably allows the detection of defects in ICs if their power exceeds some 10 µW. The imaging can be performed also through the silicon substrate from the backside of the chip. Also the well-known fluorescent microthermal imaging (FMI) technique can be be used in lock-in mode, leading to a temperature resolution in the mK range, but a spatial resolution below 1 micron.


Author(s):  
Andrew J. Komrowski ◽  
Luis A. Curiel ◽  
Daniel J. D. Sullivan ◽  
Quang Nguyen ◽  
Lisa Logan-Willams

Abstract The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.


Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]


Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.


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