scholarly journals Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

2020 ◽  
Vol 10 (8) ◽  
pp. 2979
Author(s):  
Soohyun Kim ◽  
Jungchun Kim ◽  
Doyoung Jang ◽  
Romain Ritzenthaler ◽  
Bertrand Parvais ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Temperature Dependence ◽  
Field Effect ◽  
Carrier Transport ◽  
Phonon Scattering ◽  
Field Effect Transistors ◽  
Effective Field ◽  
Temperature Dependent ◽  
Surface Roughness Scattering ◽  
Wide Range

The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of temperatures (25–125 °C). A similar temperature dependence of threshold voltage (VTH) and subthreshold swing (SS) is observed for both devices. However, effective mobility (μeff) shows significant differences of temperature dependence between GAA NW-FET and FinFET at a high gate effective field. At weak Ninv (= 5 × 1012 cm2/V∙s), both GAA NW-FET and FinFET are mainly limited by phonon scattering in μeff. On the other hand, at strong Ninv (= 1.5 × 1013 cm2/V∙s), GAA NW-FET shows 10 times higher dμeff/dT and 1.6 times smaller mobility degradation coefficient (α) than FinFET. GAA NW-FET is less limited by surface roughness scattering, but FinFET is relatively more limited by surface roughness scattering in carrier transport.

scholarly journals Temperature Dependence of Dielectric Properties of Ferroelectric Heterostructures with Domain-Provided Negative Capacitance

Nanomaterials ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 75
Author(s):  
Maksim A. Pavlenko ◽  
Yuri A. Tikhonov ◽  
Anna G. Razumnaya ◽  
Valerii M. Vinokur ◽  
Igor A. Lukyanchuk
Keyword(s):  
Phase Diagram ◽  
Dielectric Properties ◽  
Temperature Dependence ◽  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Negative Capacitance ◽  
Temperature Dependent ◽  
Domain Structures ◽  
Temperature Dependent Properties

It is well known that the ferroelectric layers in dielectric/ferroelectric/dielectric heterostructures harbor polarization domains resulting in the negative capacitance crucial for manufacturing energy-efficient field-effect transistors. However, the temperature behavior of the characteristic dielectric properties, and, hence, the corresponding behavior of the negative capacitance, are still poorly understood, restraining the technological progress thereof. Here we investigate the temperature-dependent properties of domain structures in the SrTiO3/PbTiO3/SrTiO3 heterostructures and demonstrate that the temperature–thickness phase diagram of the system includes the ferroelectric and paraelectric regions, which exhibit different responses to the applied electric field. Using phase-field modeling and analytical calculations we find the temperature dependence of the dielectric constant of ferroelectric layers and identify the regions of the phase diagram wherein the system demonstrates negative capacitance. We further discuss the optimal routes for implementing negative capacitance in energy-efficient ferroelectric field-effect transistors.

Effects of remote-surface-roughness scattering on carrier mobility in field-effect-transistors with ultrathin gate dielectrics

2004 ◽  
Vol 84 (8) ◽  
pp. 1395-1397 ◽  
Author(s):  
Shin-ichi Saito ◽  
Kazuyoshi Torii ◽  
Yasuhiro Shimamoto ◽  
Shimpei Tsujikawa ◽  
Hirotaka Hamamura ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Field Effect ◽  
Carrier Mobility ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Surface Roughness Scattering

Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 1101-1104 ◽  
Author(s):  
M.G. Jaikumar ◽  
Shreepad Karmalkar
Keyword(s):  
Surface Roughness ◽  
Measured Data ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Material Parameters ◽  
Velocity Saturation ◽  
Physical Mechanisms ◽  
Surface Roughness Scattering ◽  
Wide Range ◽  
Tcad Simulation

4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.

High-Mobility SiC MOSFETs with Alkaline Earth Interface Passivation

2016 ◽  
Vol 858 ◽  
pp. 671-676 ◽  
Author(s):  
Daniel J. Lichtenwalner ◽  
Vipindas Pala ◽  
Brett A. Hull ◽  
Scott Allen ◽  
John W. Palmour
Keyword(s):  
Nitric Oxide ◽  
Field Effect ◽  
Alkaline Earth ◽  
Phonon Scattering ◽  
Breakdown Strength ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
Alkaline Earth Elements

Alkaline earth elements Sr and Ba provide SiO2/SiC interface conditions suitable for obtaining high channel mobility metal-oxide-semiconductor field-effect-transistors (MOSFETs) on the Si-face (0001) of 4H-SiC, without the standard nitric oxide (NO) anneal. The alkaline earth elements Sr and Ba located at/near the SiO2/SiC interface result in field-effect mobility (μFE) values as high as 65 and 110 cm2/V.s, respectively, on 5×1015 cm-3 Al-doped p-type SiC. As the SiC doping increases, peak mobility decreases as expected, but the peak mobility remains higher for Ba interface layer (Ba IL) devices compared to NO annealed devices. The Ba IL MOSFET field-effect mobility decreases as the temperature is increased to 150 °C, as expected when mobility is phonon-scattering-limited, not interface-trap-limited. This is in agreement with measurements of the interface state density (DIT) using the high-low C-V technique, indicating that the Ba IL results in lower DIT than that of samples with nitric oxide passivation. Vertical power MOSFET (DMOSFET) devices (1200V, 15A) fabricated with the Ba IL have a 15% lower on-resistance compared to devices with NO passivation. The DMOSFET devices with a Ba IL maintain a stable threshold voltage under NBTI stress conditions of-15V gate bias stress, at 150 °C for 100hrs, indicating no mobile ions. Secondary-ion mass-spectrometry (SIMS) analysis confirms that the Sr and Ba remain predominantly at the SiO2/SiC interface, even after high temperature oxide annealing, consistent with the observed high channel mobility after these anneals. The alkaline earth elements result in enhanced SiC oxidation rate, and the resulting gate oxide breakdown strength is slightly reduced compared to NO annealed thermal oxides on SiC.

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