scholarly journals Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

2022 ◽  
Vol 10 (1) ◽  
pp. 732-737
Author(s):  
Prakash Sharma
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Noise Power ◽  
Ring Oscillators ◽  
Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

scholarly journals A LOW PHASE NOISE, POWER EFFICIENT VOLTAGE CONTROLLED OSCILLATOR USING 0.18-μM CMOS TECHNOLOGY

2014 ◽  
pp. 256-259
Author(s):  
AJIT SAMASGIKAR
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Sustained Oscillations ◽  
Low Phase Noise

A low phase noise, power efficient VCO using UMC 0.18μm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of -79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V - 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10% variation.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

scholarly journals Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 558 ◽  
Author(s):  
Bjorn Van Bockel ◽  
Jeffrey Prinzie ◽  
Paul Leroux
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Single Shot ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Pvt Variations ◽  
Radiation Tolerant ◽  
Radiation Measurements

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

scholarly journals Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 493
Author(s):  
Jongha Park ◽  
Jung-Hyun Park ◽  
Seong-Ook Jung
Keyword(s):  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Measurement Range ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Measurement Transducer ◽  
Current Output ◽  
Differential Nonlinearity ◽  
Rail To Rail

We propose a ring oscillator (RO) based current-to-voltage-to-frequency (I–V–F) converting current transducer with a cascade bias circuit. The I–V–F converting scheme guarantees highly stable biasing against RO, with a rail-to-rail output operation. This device was fabricated using National NanoFab Center (NNFC) 180 nm complementary metal-oxide-semiconductor (CMOS) technology, which achieves a current resolution of 1 nA in a measurement range up to 200 nA. A noise floor of 11.8 pA/√Hz, maximum differential nonlinearity (DNL) of 0.15 in 1 nA steps, and rail-to-rail output with a 1.8 V power supply is achieved. The proposed transducer can be effectively applied to bio-sensing devices requiring a compact area and low power consumption with a low current output. The fabricated structure can be applied to monolithic-three-dimensional integration with a bio-sensing device.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

scholarly journals Online Nonlinear Error Compensation Circuit Based on Neural Networks

Machines ◽  
2021 ◽  
Vol 9 (8) ◽  
pp. 151
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Chunge Ju ◽  
Qi Wei ◽  
Xinxi Zhang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Power Consumption ◽  
Inertial Sensors ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Frequency ◽  
Small Scale ◽  
Compensation Circuit

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.

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