scholarly journals A Two-Channel High-Performance DC-DC Converter for Mobile AMOLED Display Based on the PWM–SPWM Dual-Mode Switching Method

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2059
Author(s):  
Hak-Yun Kim ◽  
Tae-Un Kim ◽  
Ho-Yong Choi
Keyword(s):  
Pulse Width ◽  
Power Efficiency ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Input Voltage ◽  
Mode Switching ◽  
Light Load ◽  
Switching Node ◽  
Switching Method

In this paper, we propose a design of a two-channel high-performance DC-DC converter that provides a positive voltage VPOS with a low ripple, and a negative voltage VNEG with high power efficiency, for the purpose of enhancing power efficiency and output ripple under light loads of 100 mA or less for mobile active-matrix organic light-emitting diode (AMOLED) displays. The VPOS was designed as a boost converter using a novel input voltage variation reduction circuit (IVVRC), which rapidly changes the pulse width for input voltage fluctuations, using a feed-forward path. The VNEG was designed as an inverting buck–boost converter based on the pulse width modulation–set time variable pulse width modulation (PWM–SPWM) dual-mode switching method to enhance power efficiency, especially under light loads, and to reduce the overhead of the circuit configuration using a voltage-controlled oscillator. In addition, an adaptive dead-time using voltage detection of switching node (ADTVS) circuit was proposed to enhance power efficiency, which detects the voltage of the switching node at every cycle, and keeps the dead-time constant irrespective of changes in driving conditions. The proposed converter was fabricated with a chip size of 1.67 mm × 2.44 mm, using a 0.35 μm BCD process. Measurement results showed that the power efficiency of our converter was 72.9%~90.4% at 5 mA–100 mA light load output current, which is 2.7%~5.8% higher than the output of the previous converter. Furthermore, the output voltage ripple of VPOS and VNEG at 5 mA light load output current was 3.0 mV and 5.3 mV, respectively, which improved by 19% and 25% as compared to those of the previous converter, respectively.

scholarly journals Hybrid DC-DC Converter with Low Switching Loss, Low Primary Current and Wide Voltage Operation

Energies ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2536
Author(s):  
Bor-Ren Lin ◽  
Yi-Kuan Lin
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Input Voltage ◽  
Resonant Circuit ◽  
Switching Loss ◽  
Voltage Range ◽  
Current Loss ◽  
Zero Voltage Switching ◽  
Energy Applications ◽  
Multi Stage

A full-bridge converter with an additional resonant circuit and variable secondary turns is presented and achieved to have soft-switching operation on active devices, wide voltage input operation and low freewheeling current loss. The resonant tank is linked to the lagging-leg of the full bridge pulse-width modulation converter to realize zero-voltage switching (ZVS) characteristic on the power switches. Therefore, the wide ZVS operation can be accomplished in the presented circuit over the whole input voltage range and output load. To overcome the wide voltage variation on renewable energy applications such as DC wind power and solar power conversion, two winding sets are used on the output-side of the proposed converter to obtain the different voltage gains. Therefore, the wide voltage input from 90 to 450 V (Vin,max = 5Vin,min) is implemented in the presented circuit. To further improve the freewheeling current loss issue in the conventional phase-shift pulse-width modulation converter, an auxiliary DC voltage generated from the resonant circuit is adopted to reduce this freewheeling current loss. Compared to the multi-stage DC converters with wide input voltage range operation, the proposed circuit has a low freewheeling current loss, low switching loss and a simple control algorithm. The studied circuit is tested and the experimental results are demonstrated to testify the performance of the resented circuit.

Modelling and analysis of a high-performance Class D audio amplifier using unipolar pulse-width-modulation

2012 ◽  
Vol 99 (2) ◽  
pp. 163-177 ◽  
Author(s):  
Zekun Zhou ◽  
Yue Shi ◽  
Xin Ming ◽  
Bo Zhang ◽  
Zhaoji Li ◽  
...  
Keyword(s):  
Pulse Width ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Audio Amplifier ◽  
Class D ◽  
Unipolar Pulse

scholarly journals A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2195
Author(s):  
Jin-Wook Kang ◽  
Seung-Wook Hyun ◽  
Yong Kan ◽  
Hoon Lee ◽  
Jung-Hyo Lee
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Short Circuit ◽  
Reference Voltage ◽  
Voltage Source ◽  
Switching Operation ◽  
Voltage Unbalance ◽  
Offset Voltage ◽  
Simulation And Experiment

This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented.

Simulation Study of SVPWM Control Technology for NPC Inverter

2013 ◽  
Vol 347-350 ◽  
pp. 392-395
Author(s):  
Song Li
Keyword(s):  
Pulse Width ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Electronic Devices ◽  
Multilevel Inverter ◽  
Control Technology ◽  
Power Electronic ◽  
Structure Characteristics ◽  
The World ◽  
Working Principle

With the development of high voltage technology ,the inverter power is becoming higher and higher . The traditional two-level inverter capacity has been difficult to achieve high power requirements due to the limitation of the power electronic devices. Therefore, different new kinds of multilevel inverter topologies with high-performance are proposed by the scientist all over the world. This paper introduces the topology structure, characteristics and working principle of threelevel inverter, and makes a detailed description of space vector pulse width modulation principle. Finally, the simulation waveforms are presented with Matlab/Simulink, the results verifies the validity of the theoretical analysis.

Synchronized Symmetrical Bus-Clamping PWM Strategies for Three Level Inverter: Applications to Low Switching Frequencies

2011 ◽  
Vol 12 (2) ◽  
Author(s):  
Sreenivasappa Bhupasandra Veeranna ◽  
Udaykumar R Yaragatti ◽  
Abdul R Beig
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Industrial Applications ◽  
Voltage Source ◽  
Switching Frequency ◽  
Space Vector ◽  
Digital Implementation ◽  
Switching Losses

The digital control of three-level voltage source inverter fed high power high performance ac drives has recently become a popular in industrial applications. In order to control such drives, the pulse width modulation algorithm needs to be implemented in the controller. In this paper, synchronized symmetrical bus-clamping pulse width modulation strategies are presented. These strategies have some practical advantages such as reduced average switching frequency, easy digital implementation, reduced switching losses and improved output voltage quality compared to conventional space vector pulse width modulation strategies. The operation of three level inverter in linear region is extended to overmodulation region. The performance is analyzed in terms THD and fundamental output voltage waveforms and is compared with conventional space vector PWM strategies and found that switching losses can be minimized using bus-clamping strategy compared to conventional space vector strategy. The proposed method is implemented using Motorola Power PC 8240 processor and verified on a constant v/f induction motor drive fed from IGBT based inverter.

Research on a Novel Non Dead-Time Compensation Two-Phase Modulation SVPWM Control Strategy

2012 ◽  
Vol 546-547 ◽  
pp. 1050-1055
Author(s):  
Bao Lian Liu ◽  
De Fei Jin
Keyword(s):  
Control Strategy ◽  
Phase Modulation ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Modulation Method ◽  
Two Phase ◽  
Switching Losses ◽  
Dead Time Compensation ◽  
Switching State

A space vector pulse-width modulation (SVPWM) strategy was developed to solve the failure of traditional SVPWM. A two-phase modulation method is adopted basing on the analyses of traditional SVPWM to select the null switching state in each sector according to the power factor angle. As a result, when the current is crossing zero, the corresponding phase does not commute and dead-time compensation is avoided; and when the current is nearing the peak, the corresponding phase also don’t commute, which leads to lower switching losses. The simulation and experimental results validate that the proposed strategy can effectively improve the current wave, minimize the current distortion and reduce the switching losses. Furthermore, the algorithm is easy to implement.

Investigation on positioning control strategy and switching optimization of an equal coded digital valve system

2019 ◽  
Vol 234 (8) ◽  
pp. 959-972
Author(s):  
Qiang Gao ◽  
Matti Linjama ◽  
Miika Paloniitty ◽  
Yuchuan Zhu
Keyword(s):  
Cost Function ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Differential Pulse ◽  
Pulse Number ◽  
Equal Distribution ◽  
Positioning Control ◽  
Valve System ◽  
Circular Buffer ◽  
Switching Method

This article concerns high accuracy positioning control with switching optimization for an equal coded digital valve system. Typically, pulse number modulation control cannot realize micro-positioning due to the characteristics of step-wise flow variation, therefore, a new position controller consisting of a model-based pulse number modulation and a differential pulse width modulation strategy is proposed to control the position of a hydraulic cylinder at high and low velocity cases, respectively. In addition, in order to solve several problems caused by the pulse number modulation and differential pulse width modulation, such as increased number of switchings and large difference among number of switchings of valves, a switching optimization consisting of a switching cost function, a circular buffer and a circular switching method is proposed. An adaptive weight of the switching cost function is proposed for the first time to reduce the total number of switchings under different pressure differences and its design criterion is presented. A circular buffer and a new circular switching method are used to improve the degree of equal distribution of switchings when the pulse number modulation and differential pulse width modulation are used, respectively. Comparative experimental results indicated that the average and the minimum positioning error for the proposed controller are only 10 and 1 μm, respectively. The number of switchings and the degree of equal distribution of switchings are significantly optimized. Moreover, the pressure fluctuations caused by the proposed controller remain acceptable.

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