A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
Keyword(s):
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm2. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.
2014 ◽
Vol 23
(05)
◽
pp. 1450057
2019 ◽
Vol 8
(11S)
◽
pp. 11-19
Keyword(s):
2015 ◽
Vol 34
(8)
◽
pp. 2419-2439
◽
2007 ◽
Vol 16
(01)
◽
pp. 1-14
2022 ◽
2012 ◽
Vol 2012
(HITEC)
◽
pp. 000245-000252
◽