scholarly journals Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

2021 ◽  
Author(s):  
Michal Sovcik ◽  
Lukas Nagy ◽  
Viera Stopjakova ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic System ◽  
Digital Calibration ◽  
Electrical Stress ◽  
Offset Voltage ◽  
On Chip ◽  
Analog Systems

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600 mV with 10% variation, in temperature range from − 20 ° C to 85 ° C . Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13 μV to 167 μV . With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

scholarly journals Interband Cascade Photonic Integrated Circuits on Native III-V Chip

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 599
Author(s):  
Jerry R. Meyer ◽  
Chul Soo Kim ◽  
Mijin Kim ◽  
Chadwick L. Canedy ◽  
Charles D. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Laser Cavity ◽  
Building Blocks ◽  
Drive Power ◽  
Optical Elements ◽  
Photonic Integrated Circuit ◽  
Cleaved Facets ◽  
On Chip

We describe how a midwave infrared photonic integrated circuit (PIC) that combines lasers, detectors, passive waveguides, and other optical elements may be constructed on the native GaSb substrate of an interband cascade laser (ICL) structure. The active and passive building blocks may be used, for example, to fabricate an on-chip chemical detection system with a passive sensing waveguide that evanescently couples to an ambient sample gas. A variety of highly compact architectures are described, some of which incorporate both the sensing waveguide and detector into a laser cavity defined by two high-reflectivity cleaved facets. We also describe an edge-emitting laser configuration that optimizes stability by minimizing parasitic feedback from external optical elements, and which can potentially operate with lower drive power than any mid-IR laser now available. While ICL-based PICs processed on GaSb serve to illustrate the various configurations, many of the proposed concepts apply equally to quantum-cascade-laser (QCL)-based PICs processed on InP, and PICs that integrate III-V lasers and detectors on silicon. With mature processing, it should become possible to mass-produce hundreds of individual PICs on the same chip which, when singulated, will realize chemical sensing by an extremely compact and inexpensive package.

scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits

2013 ◽  
Vol 10 (4) ◽  
pp. 155-162 ◽  
Author(s):  
L. Lanni ◽  
B. G. Malm ◽  
C.-M. Zetterling ◽  
M. Östling
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Bipolar Transistors ◽  
Digital Integrated Circuits ◽  
Successful Operation ◽  
Bipolar Technology ◽  
Propagation Delays ◽  
Interconnect Systems

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits

2013 ◽  
Author(s):  
Franco Stellari ◽  
Alan J. Weger ◽  
Seongwon Kim ◽  
Dzmitry Maliuk ◽  
Peilin Song ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Single Photon ◽  
Vlsi Circuits ◽  
Photon Detector ◽  
Single Photon Detector ◽  
Time Resolved ◽  
Superconducting Nanowire ◽  
Emission Light

Abstract In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.

SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure

2021 ◽  
Vol 17 (3) ◽  
pp. 1-28
Author(s):  
Shubhra Deb Paul ◽  
Swarup Bhunia
Keyword(s):  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Supply Voltage ◽  
Semiconductor Industry ◽  
Electronic System ◽  
Circuit Board ◽  
System Level ◽  
Printed Circuit ◽  
Industry Standard ◽  
Custom Hardware

A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn  is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn  also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.

scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

NQR Spectrometer with a Two Integrated Circuits Radio Frequency Head

1990 ◽  
Vol 45 (3-4) ◽  
pp. 591-594 ◽  
Author(s):  
Yushi Zikumaru
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Radio Frequency Voltage

Abstract An NQR spectrometer has been constructed using two linear integrated circuits in its oscillator-detector. This is very simple and compact and works in range 3-65 MHz. The radio frequency voltage can be varied from 10 mVp-p to 15 V p-p by changing the supply-voltage of an integrated circuit μA 733. The utility of the spectrometer is demonstrated by recording 35Cl NQR spectra in p-C6H4Cl2 , NaClO3 , and KClO3 .

scholarly journals Fully-integrated LDO voltage regulator for digital circuits

2011 ◽  
Vol 9 ◽  
pp. 263-267 ◽  
Author(s):  
M. Lüders ◽  
B. Eversmann ◽  
D. Schmitt-Landsiedel ◽  
R. Brederlow
Keyword(s):  
Digital Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Maximum Load ◽  
Voltage Regulators ◽  
Ultra Low Power ◽  
Fully Integrated ◽  
Large Current ◽  
Quiescent Current ◽  
On Chip

Abstract. Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 μm test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 μA.

scholarly journals Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 62 ◽  
Author(s):  
Joakim Nilsson ◽  
Johan Borg ◽  
Jonny Johansson
Keyword(s):  
Integrated Circuits ◽  
Process Parameters ◽  
Integrated Circuit ◽  
Q Factor ◽  
Worst Case ◽  
Circuit Topology ◽  
Equivalent Capacitance ◽  
On Chip ◽  
Bond Pads ◽  
The Given

This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.

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