scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

scholarly journals A Review on Terahertz Technologies Accelerated by Silicon Photonics

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1646
Author(s):  
Jingya Xie ◽  
Wangcheng Ye ◽  
Linjie Zhou ◽  
Xuguang Guo ◽  
Xiaofei Zang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Silicon Photonics ◽  
Large Scale ◽  
Cost Effective ◽  
Single Chip ◽  
Photonic Integrated Circuit ◽  
Hybrid Silicon ◽  
The Cost ◽  
Silicon Based ◽  
Thz Applications

In the last couple of decades, terahertz (THz) technologies, which lie in the frequency gap between the infrared and microwaves, have been greatly enhanced and investigated due to possible opportunities in a plethora of THz applications, such as imaging, security, and wireless communications. Photonics has led the way to the generation, modulation, and detection of THz waves such as the photomixing technique. In tandem with these investigations, researchers have been exploring ways to use silicon photonics technologies for THz applications to leverage the cost-effective large-scale fabrication and integration opportunities that it would enable. Although silicon photonics has enabled the implementation of a large number of optical components for practical use, for THz integrated systems, we still face several challenges associated with high-quality hybrid silicon lasers, conversion efficiency, device integration, and fabrication. This paper provides an overview of recent progress in THz technologies based on silicon photonics or hybrid silicon photonics, including THz generation, detection, phase modulation, intensity modulation, and passive components. As silicon-based electronic and photonic circuits are further approaching THz frequencies, one single chip with electronics, photonics, and THz functions seems inevitable, resulting in the ultimate dream of a THz electronic–photonic integrated circuit.

scholarly journals Interband Cascade Photonic Integrated Circuits on Native III-V Chip

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 599
Author(s):  
Jerry R. Meyer ◽  
Chul Soo Kim ◽  
Mijin Kim ◽  
Chadwick L. Canedy ◽  
Charles D. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Laser Cavity ◽  
Building Blocks ◽  
Drive Power ◽  
Optical Elements ◽  
Photonic Integrated Circuit ◽  
Cleaved Facets ◽  
On Chip

We describe how a midwave infrared photonic integrated circuit (PIC) that combines lasers, detectors, passive waveguides, and other optical elements may be constructed on the native GaSb substrate of an interband cascade laser (ICL) structure. The active and passive building blocks may be used, for example, to fabricate an on-chip chemical detection system with a passive sensing waveguide that evanescently couples to an ambient sample gas. A variety of highly compact architectures are described, some of which incorporate both the sensing waveguide and detector into a laser cavity defined by two high-reflectivity cleaved facets. We also describe an edge-emitting laser configuration that optimizes stability by minimizing parasitic feedback from external optical elements, and which can potentially operate with lower drive power than any mid-IR laser now available. While ICL-based PICs processed on GaSb serve to illustrate the various configurations, many of the proposed concepts apply equally to quantum-cascade-laser (QCL)-based PICs processed on InP, and PICs that integrate III-V lasers and detectors on silicon. With mature processing, it should become possible to mass-produce hundreds of individual PICs on the same chip which, when singulated, will realize chemical sensing by an extremely compact and inexpensive package.

A WDM receiver photonic integrated circuit with net on-chip gain

1994 ◽  
Vol 6 (8) ◽  
pp. 960-962 ◽  
Author(s):  
J.-M. Verdiell ◽  
T.L. Koch ◽  
B.I. Miller ◽  
M.E. Young ◽  
U. Koren ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Photonic Integrated Circuit ◽  
On Chip

Silicon photonic integrated circuit for on-chip spectroscopic gas sensing

2019 ◽  
Author(s):  
Chi Xiong ◽  
Yves Martin ◽  
Eric J. Zhang ◽  
Jason S. Orcutt ◽  
Martin Glodde ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Gas Sensing ◽  
Photonic Integrated Circuit ◽  
Silicon Photonic ◽  
On Chip

scholarly journals Templated dewetting of single-crystal sub-millimeter-long nanowires and on-chip silicon circuits

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Monica Bollani ◽  
Marco Salvalaglio ◽  
Abdennacer Benali ◽  
Mohammed Bouabdellaoui ◽  
Meher Naffouti ◽  
...  
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Spontaneous Formation ◽  
Surface Energy Anisotropy ◽  
Energy Anisotropy ◽  
On Chip ◽  
Silicon Based ◽  
Nano Wires

AbstractLarge-scale, defect-free, micro- and nano-circuits with controlled inter-connections represent the nexus between electronic and photonic components. However, their fabrication over large scales often requires demanding procedures that are hardly scalable. Here we synthesize arrays of parallel ultra-long (up to 0.75 mm), monocrystalline, silicon-based nano-wires and complex, connected circuits exploiting low-resolution etching and annealing of thin silicon films on insulator. Phase field simulations reveal that crystal faceting and stabilization of the wires against breaking is due to surface energy anisotropy. Wires splitting, inter-connections and direction are independently managed by engineering the dewetting fronts and exploiting the spontaneous formation of kinks. Finally, we fabricate field-effect transistors with state-of-the-art trans-conductance and electron mobility. Beyond the first experimental evidence of controlled dewetting of patches featuring a record aspect ratio of $$\sim$$~1/60000 and self-assembled $$\sim$$~mm long nano-wires, our method constitutes a distinct and promising approach for the deterministic implementation of atomically-smooth, mono-crystalline electronic and photonic circuits.

scholarly journals A Comparison between off and On-Chip Injection Locking in a Photonic Integrated Circuit

Photonics ◽  
2019 ◽  
Vol 6 (4) ◽  
pp. 103 ◽  
Author(s):  
Alison Perrott ◽  
Ludovic Caro ◽  
Mohamad Dernaika ◽  
Frank Peters
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Power Spectra ◽  
Dynamical Behaviour ◽  
Injection Locking ◽  
Semiconductor Diode ◽  
Photonic Integrated Circuit ◽  
Semiconductor Diode Laser ◽  
Spectrum Analyser ◽  
On Chip

The mutual and injection locking characteristics of two integrated lasers are compared, both on and off-chip. In this study, two integrated single facet slotted Fabry–Pérot lasers are utilised to develop the measurement technique used to examine the different operational regimes arising from optically locking a semiconductor diode laser. The technique employed used an optical spectrum analyser (OSA), an electrical spectrum analyser (ESA) and a high speed oscilloscope (HSO). The wavelengths of the lasers are measured on the OSA and the selected optical mode for locking is identified. The region of injection locking and various other regions of dynamical behaviour between the lasers are observed on the ESA. The time trace information of the system is obtained from the HSO and performing the FFT (Fast Fourier Transform) of the time traces returns the power spectra. Using these tools, the similarities and differences between off-chip injection locking with an isolator, and on-chip mutual locking are examined.

A Comprehensive Test Compression Scheme Based on Precomputed Test Sets

2013 ◽  
Vol 756-759 ◽  
pp. 533-541
Author(s):  
Zhi Jian Tian ◽  
Fa Yong Zhao
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Test Pattern ◽  
Compression Scheme ◽  
Run Length ◽  
Rearrangement Algorithm ◽  
Long Run ◽  
Assignment Strategy ◽  
Run Lengths

To cope with increasingly rigorous challenges that large scale digital integrated circuit testing is confronted with, a comprehensive compression scheme consisting of test-bit rearrangement algorithm, run-length assignment strategy and symmetrical code is proposed. The presented test-bit rearrangement algorithm can fasten dont-care bits, 0s or 1s in every test pattern on one of its end to the greatest extent so as to lengthen end-run blocks and decrease number of short run-lengths. A dynamical dont-care assignment strategy based on run-lengths can be used to specify the remaining dont-care bits after the test-bit rearrangement, which can decrease run-length splitting and maximize length of run-lengths. The symmetrical code benefits from long run-lengths and only uses 2 4-bit short code words to identify end-run blocks almost as long as a test pattern, and hence the utilization ratio of code words can be heightened. The presented experiment results show that the proposed comprehensive scheme can obtain very higher data compression ratios than other compression ones published up to now, especially for large scale digital integrated circuits, and considerably decrease test power dissipations.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

scholarly journals Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

2019 ◽  
Vol 9 (20) ◽  
pp. 4212 ◽  
Author(s):  
Mingqiang Huang ◽  
Xingli Wang ◽  
Guangchao Zhao ◽  
Philippe Coquet ◽  
Bengkang Tay
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
2D Materials ◽  
Two Dimensional ◽  
Ternary Logic ◽  
Chip Area ◽  
Logic Devices ◽  
Ripple Carry Adder ◽  
Data Density

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

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