scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

scholarly journals A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 375
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Adaptive Power

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

scholarly journals Design and Characteristics of CMOS Inverter based on Multisim and Cadence

2021 ◽  
Vol 2108 (1) ◽  
pp. 012034
Author(s):  
Haoran Xu ◽  
Jianghua Ding ◽  
Jian Dang
Keyword(s):  
Metal Oxide ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Data Converters ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
And Performance

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

Silicon-Based Microphotonics and Integrated Optoelectronics

MRS Bulletin ◽  
1998 ◽  
Vol 23 (4) ◽  
pp. 39-47 ◽  
Author(s):  
E.A. Fitzgerald ◽  
L.C. Kimerling
Keyword(s):  
Driving Force ◽  
Complementary Metal Oxide Semiconductor ◽  
Electronic System ◽  
Cmos Technology ◽  
Labor Cost ◽  
Oxide Semiconductor ◽  
Electronic Systems ◽  
Remarkable Feature ◽  
And Performance ◽  
The Cost

The need for integrated optical interconnects in electronic systems is derivedfrom the cost and performance of electronic systems. If we examine the cost of all interconnects, it becomes apparent that there is an exponential growth in cost per interconnect with the length of the interconnect. A remarkable feature of interconnect cost is that the exponential relation holds over all length scales—from the shortest interconnects on a chip to the longest interconnects in global telecommunications networks. Longer interconnects are drastically more expensive, and these costs are ultimately related to the labor cost associated with each interconnect. Given this economic pressure, it is not surprising that there is a driving force to condense more functions locally on the same chip, board, or system. In condensing these functions, the number of long interconnects are decreased and the overall cost of the electronic system decreases dramatically. A specific glaring example of this driving force is Si complementary-metal-oxide-semiconductor (CMOS) technology, especially the case of microprocessors. In the Si microprocessor case, the flood gates to interconnect condensation were opened and the miraculous trend of lower cost for exponentially increasing performance was revealed.

scholarly journals Design and analysis of current mirror OTA in 45 nm and 90 nm CMOS technology for bio-medical application

2020 ◽  
Vol 9 (1) ◽  
pp. 221-228
Author(s):  
Wan Mohammad Ehsan Aiman Wan Jusoh ◽  
Siti Hawa Ruslan
Keyword(s):  
Detection System ◽  
Complementary Metal Oxide Semiconductor ◽  
Medical Application ◽  
Cmos Technology ◽  
Open Loop ◽  
Oxide Semiconductor ◽  
Current Mirror ◽  
Ecg Signals ◽  
Transconductance Amplifier ◽  
And Performance

This paper proposed a design and performance analysis of current mirror operational transconductance amplifier (OTA) in 45 nm and 90 nm complementary metal oxide semiconductor (CMOS) technology for bio-medical application. Both OTAs were designed and simulated using Synopsys tools and the simulation results were analysed thoroughly. The OTAs were designed to be implemented in bio-potential signals detection system where the input signals were amplified and filtered according to the specifications. From the comparative analysis of both OTAs, the 45 nm OTA managed to produce open loop gain of 45 dB, with common mode rejection ratio (CMRR) of 93.2 dB. The 45 nm OTA produced only 1.113 μV√Hz of input referred noise at 1 Hz. The 45 nm OTA also consumed only 28.21 nW of power from ± 0.5 V supply. The low-power consumption aspect displayed by 45 nm OTA made it suitable to be implemented in bio-medical application such as bio-potential signals detection system where it can be used to amplify and filter the electrocardiogram (ECG) signals.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals A High-Performance Elliptic Curve Cryptographic Processor of SM2 over GF(p)

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 431 ◽  
Author(s):  
Xianghong Hu ◽  
Xin Zheng ◽  
Shengshi Zhang ◽  
Weijun Li ◽  
Shuting Cai ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Prime Field ◽  
Practical Applications ◽  
Public Key Cryptosystems ◽  
Cell Library ◽  
Multiplication Operation ◽  
And Performance

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

scholarly journals Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 477 ◽  
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md Torikul Islam Badal ◽  
Mamun Bin Ibne Reaz ◽  
Maria Liz Crespo ◽  
Andres Cicuttin
Keyword(s):  
Output Power ◽  
High Performance ◽  
High Efficiency ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hot Electron ◽  
Oxide Breakdown ◽  
Rf Signals ◽  
Hot Electron Effect

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

scholarly journals High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 579 ◽  
Author(s):  
Martín Riverola ◽  
Francesc Torres ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Life Time ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Mechanical Contact ◽  
Contact Materials ◽  
Monolithically Integrated ◽  
Cmos Mems ◽  
Mechanical Logic

In this paper, a seesaw torsional relay monolithically integrated in a standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology is presented. The seesaw relay is fabricated using the Back-End-Of-Line (BEOL) layers available, specifically using the tungsten VIA3 layer of a 0.35 μm CMOS technology. Three different contact materials are studied to discriminate which is the most adequate as a mechanical relay. The robustness of the relay is proved, and its main characteristics as a relay for the three different contact interfaces are provided. The seesaw relay is capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. The low contact resistance achieved with the TiN/W mechanical contact with high cycling life time is competitive in comparison with the state-of-the art.

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