scholarly journals Proton Induced Single Event Effect Characterization on a Highly Integrated RF-Transceiver

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 519 ◽  
Author(s):  
Jan Budroweit ◽  
Mattis Paul Jaksch ◽  
Maciej Sznajder
Keyword(s):  
Radio Frequency ◽  
Integrated Circuit ◽  
Digital Signal ◽  
Single Event ◽  
Rf Transceiver ◽  
Space Applications ◽  
Radio System ◽  
Filter Bandwidth ◽  
Single Event Effect ◽  
High Level

Radio frequency (RF) systems in space applications are usually designed for a single task and its requirements. Flexibility is mostly limited to software-defined adaption of the signal processing in digital signal processors (DSP) or field-programmable gate arrays (FPGA). RF specifications, such as frequency band selection or RF filter bandwidth are thereby restricted to the specific application requirements. New radio frequency integrated circuit (RFIC) devices also allow the software-based reconfiguration of various RF specifications. A transfer of this RFIC technology to space systems would have a massive impact to future radio systems for space applications. The benefit of this RFIC technology allows a selection of different RF radio applications, independent of their RF parameters, to be executed on a single unit and, thus, reduces the size and weight of the whole system. Since most RF application sin space system require a high level of reliability and the RFIC is not designed for the harsh environment in space, a characterization under these special environmental conditions is mandatory. In this paper, we present the single event effect (SEE) characterization of a selected RFIC device under proton irradiation. The RFIC being tested is immune to proton induced single event latch-up and other destructive events and shows a very low response to single failure interrupts. Thus, the device is defined as a good candidate for future, highly integrated radio system in space applications.

VLSI for Space Applications—Single Event Effect Investigation and Optical Analysis on an Integrated Laser Platform

2017 ◽  
Author(s):  
Samuel Chef ◽  
Chung Tah Chua ◽  
Yu Wen Siah ◽  
Philippe Perdu ◽  
Chee Lip Gan ◽  
...  
Keyword(s):  
Pulsed Laser ◽  
Single Event ◽  
Optical Analysis ◽  
Space Applications ◽  
Laser Probing ◽  
Single Event Effect ◽  
Evaluation Time ◽  
Black Boxes ◽  
System Use ◽  
First Time

Abstract Today’s VLSI devices are neither designed nor manufactured for space applications in which single event effects (SEE) issues are common. In addition, very little information about the internal schematic and usually nothing about the layout or netlist is available. Thus, they are practically black boxes for satellite manufacturers. On the other hand, such devices are crucial in driving the performance of spacecraft, especially smaller satellites. The only way to efficiently manage SEE in VLSI devices is to localize sensitive areas of the die, analyze the regions of interest, study potential mitigation techniques, and evaluate their efficiency. For the first time, all these activities can be performed using the same tool with a single test setup that enables a very efficient iterative process that reduce the evaluation time from months to days. In this paper, we will present the integration of a pulsed laser for SEE study into a laser probing, laser stimulation, and emission microscope system. Use of this system will be demonstrated on a commercial 8 bit microcontroller.

Highly Integrated Radar Sensor-on-Chip

Frequenz ◽  
2012 ◽  
Vol 66 (5-6) ◽  
Author(s):  
Ralph Mende
Keyword(s):  
Radio Frequency ◽  
System Design ◽  
Integrated Circuit ◽  
Digital Signal Processor ◽  
Silicon Germanium ◽  
Digital Signal ◽  
Radar System ◽  
Radar Sensor ◽  
Shift Keying ◽  
And Performance

AbstractA highly integrated 24 GHz radar sensor is presented, based on a Radio Frequency Integrated Circuit (RFIC) which was specifically developed for a Frequency Modulated Shift Keying (FMSK) based Radar system design. Antenna, waveform, the Radio Frequency (RF) and Digital Signal Processor (DSP) module, the software design, cost and performance aspects will be described. The significant technical and economical advantages of the implemented Silicon-Germanium (SiGe) Bipolar CMOS (BiCMOS) transceiver are demonstrated. Some automotive and other applications based on this technology and new radar system design will be explained.

Failure Analysis of CDM-ESD Damage in a GaAs RFIC

2000 ◽  
Author(s):  
Amy Poe ◽  
Steve Brockett ◽  
Tony Rubalcava
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Production Test ◽  
Analysis Techniques ◽  
Device Model ◽  
Charged Device ◽  
Subsequent Failure

Abstract The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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