scholarly journals High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 725
Author(s):  
Xiaoran Li ◽  
Jian Gao ◽  
Zhiming Chen ◽  
Xinghua Wang
Keyword(s):  
Low Power ◽  
High Speed ◽  
Single Phase ◽  
Logic Gates ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Operating Frequency ◽  
Wide Range ◽  
Measurement Results ◽  
Phase Clock

This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

scholarly journals A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

2017 ◽  
Vol 14 (1) ◽  
pp. 20160446-20160446 ◽  
Author(s):  
Wenjian Jiang ◽  
Fengqi Yu ◽  
Qinjin Huang
Keyword(s):  
Low Power ◽  
High Speed ◽  
Single Phase ◽  
Phase Clock

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

scholarly journals Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Shikha Panwar ◽  
Mayuresh Piske ◽  
Aatreya Vivek Madgula
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Circuits ◽  
Output Node ◽  
Critical Sections

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

scholarly journals DFAL: Diode-Free Adiabatic Logic Circuits

2013 ◽  
Vol 2013 ◽  
pp. 1-12 ◽  
Author(s):  
Shipra Upadhyay ◽  
R. A. Mishra ◽  
R. K. Nagaria ◽  
S. P. Singh
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Mathematical Expression ◽  
Logic Gates ◽  
Cmos Technology ◽  
Circuit Performance ◽  
Adiabatic Circuit ◽  
Output Amplitude ◽  
Adiabatic Logic

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

scholarly journals FAST LOW POWER FREQUENCY SYNTHESIS APPLICATIONS BY USING A DCVSL DELAY CELL

2015 ◽  
pp. 220-225
Author(s):  
N. KUMAR BABU ◽  
P. SASIBALA
Keyword(s):  
Low Power ◽  
High Speed ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Model Parameters ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Delay Cell ◽  
Parasitic Effects

In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.

scholarly journals A low-power high-speed true single phase clock divide-by-2/3 prescaler

2013 ◽  
Vol 10 (2) ◽  
pp. 20120913-20120913 ◽  
Author(s):  
Jianhui Wu ◽  
Zixuan Wang ◽  
Xincun Ji ◽  
Cheng Huang
Keyword(s):  
Low Power ◽  
High Speed ◽  
Single Phase ◽  
Phase Clock
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