scholarly journals Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1585
Author(s):  
Hanbin Wang ◽  
Jinshun Bi ◽  
Mengxin Liu ◽  
Tingting Han
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Gate Structure ◽  
Different Temperatures ◽  
Dual Gate ◽  
Sensitivity Changes ◽  
Increasing Temperature ◽  
Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

scholarly journals LoGHeD: An effective approach for negative differential resistance effect suppression in negative capacitance transistors

2022 ◽  
Author(s):  
Ziqiang Xie ◽  
Weifeng Lyu ◽  
Mengxue Guo ◽  
Mengjie Zhao
Keyword(s):  
Negative Differential Resistance ◽  
Computer Aided Design ◽  
Differential Resistance ◽  
Silicon On Insulator ◽  
Negative Capacitance ◽  
Fully Depleted ◽  
In Doping ◽  
Drain Side ◽  
Negative Differential Resistance Effect ◽  
Aided Design

Abstract A negative capacitance transistor (NCFET) with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design (TCAD) simulation results have validated that the output conductance (GDS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (VTH), sub-threshold swing (SS), switching current ratio (ION/IOFF), and drain-induced barrier lowering (DIBL).

scholarly journals Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations

Sensors ◽  
2020 ◽  
Vol 20 (14) ◽  
pp. 3946
Author(s):  
Linjie Fan ◽  
Jinshun Bi ◽  
Kai Xi ◽  
Gangping Yan
Keyword(s):  
Computer Aided Design ◽  
Radiation Effects ◽  
Heavy Ion ◽  
Silicon On Insulator ◽  
Voltage Sensitivity ◽  
Hall Voltage ◽  
Fully Depleted ◽  
Offset Voltage ◽  
Hall Sensors ◽  
Tcad Simulations

This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event transient (SET) effects. Via 3D technology computer aided design (TCAD) simulations with insulator fixed charge, radiation, heavy ion, and galvanomagnetic transport models, the performances of the transient current, Hall voltage, sensitivity, efficiency, and offset voltage have been evaluated. For the TID effect, the Hall voltage and sensitivity of the sensor increase after irradiation, while the efficiency and offset voltage decrease. As for TDR and SET effects, when the energy deposited on the sensor during a nuclear explosion or heavy ion injection is small, the transient Hall voltage of the off-state sensor first decreases and then returns to the initial value. However, if the energy deposition is large, the transient Hall voltage first decreases, then increases to a peak value and decreases to a fixed value. The physical mechanisms that produce different trends in the transient Hall voltage have been analyzed in detail.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

scholarly journals A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1198
Author(s):  
Han Li ◽  
Chen Wang ◽  
Lin Chen ◽  
Hao Zhu ◽  
Qingqing Sun
Keyword(s):  
Computer Aided Design ◽  
Random Access ◽  
Floating Gate ◽  
Silicon On Insulator ◽  
Semiconductor Electronic ◽  
Floating Gate Memory ◽  
Retention Characteristics ◽  
Tcad Simulation ◽  
Aided Design ◽  
Physical Challenges

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

scholarly journals MFMIS Negative Capacitance FinFET Design for Improving Drive Current

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1423
Author(s):  
Jinhong Min ◽  
Changhwan Shin
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Parasitic Capacitance ◽  
Negative Capacitance ◽  
Gate Leakage Current ◽  
Drive Current ◽  
Aided Design ◽  
Voltage Degradation ◽  
Coercive Electric Field ◽  
Threshold Voltage Degradation

The effect of remnant polarization (Pr), coercive electric-field (Ec), and parasitic capacitance of baseline device on the drive current (ION) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was investigated. The internal gate voltage in the MFMIS structure was simulated considering gate leakage current. Using technology computer aided design (TCAD) tool, the device characteristic of 7 nm FinFET was quantitatively estimated, for the purpose of modeling the baseline device of MFMIS NC FinFET. The need for appropriate parasitic capacitance to avoid performance degradation in MFMIS NC FinFET was presented through the internal gate voltage estimation. With an appropriate parasitic capacitance, the effect of Pr and Ec was investigated. In the case of Ec engineering, it is inappropriate to improve the device performance for MFMIS NC FinFET without threshold voltage degradation. Rather than Ec engineering, an adequate Pr value for achieving high ION in MFMIS NC FinFET is suggested.

Surrounding Channel Nanowire Tunnel Field-Effect Transistor with Dual Gate to Reduce a Hump Phenomenon

2020 ◽  
Vol 20 (7) ◽  
pp. 4182-4187
Author(s):  
Ye Sung Kwon ◽  
Seong-Hyun Lee ◽  
Yoon Kim ◽  
Garam Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Control Device ◽  
Subthreshold Region ◽  
Dual Gate ◽  
Technical Issues ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) with surrounding channel nanowire (SCNW) structure promises better performance than the conventional planar TFET in terms of subthreshold swing (SS) and on-current (ION). In spite of the advantages of SCNW TFET, there are some technical issues in the aspects of a hump phenomenon in subthreshold region and a high ambipolar current (IAMB) in off-state. In order to overcome these issues, a novel dual-gate SCNW TFET (DG-SCNW TFET) with differential gate work functions (WFs) and a gate-drain underlap is proposed and studied by using technology computer-aided design (TCAD) simulation. In addition, a hetero-junction with SiGe source is applied to improve the device performance. Finally, it is confirmed that the optimized DG-SCNW TFET shows the remarkable performance comparing with the control device.

scholarly journals Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1415 ◽  
Author(s):  
Jaehong Lee ◽  
Garam Kim ◽  
Sangwan Kim
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Gate Bias ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on–off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

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