scholarly journals Sector Subdivision Based SVPWM Strategy of Neutral-Point-Clamped Three-Level Inverter for Current Ripple Reduction

Energies ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2734 ◽  
Author(s):  
Guozheng Zhang ◽  
Bingxu Wei ◽  
Xin Gu ◽  
Xinmin Li ◽  
Zhanqing Zhou ◽  
...  
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Small Region ◽  
Output Current ◽  
Switching Sequence ◽  
Output Performance ◽  
Ripple Reduction ◽  
Average Current ◽  
Current Ripple ◽  
Continuous Pulse

This paper presents a sector subdivision based space vector pulse width modulation (SVPWM) strategy with reduced current ripple for a three-level inverter. Using the output current ripple theory, closed-form expressions of average current ripple vectors for both continuous and discontinuous switching sequences are derived. Based on the sector and triangle distributions of conventional SVPWM strategy, each triangle is further divided into three small-regions. Then the switching sequence with the lowest magnitude of the average current ripple vector is applied in every small-region, so that the advantages of continuous pulse width modulation (CPWM) and discontinuous pulse width modulation (DPWM) under different modulation index conditions are combined to reduce the current ripple in the whole modulation range. The output performance of the proposed strategy is compared with the conventional CPWM and DPWM strategy, and experimental results verify that the proposed strategy could reduce the current ripple of three-level inverters effectively.

Optimal space vector pulse width modulation strategy of neutral point clamped three‐level inverter for output current ripple reduction

2017 ◽  
Vol 10 (12) ◽  
pp. 1638-1646 ◽  
Author(s):  
Wei Chen ◽  
Wenkai Dai ◽  
Zhiqiang Wang ◽  
Guozheng Zhang ◽  
Yan Yan ◽  
...  
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Neutral Point ◽  
Output Current ◽  
Space Vector ◽  
Ripple Reduction ◽  
Optimal Space ◽  
Current Ripple

scholarly journals Common Mode Voltage Elimination for Quasi-Switch Boost T-Type Inverter Based on SVM Technique

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 76 ◽  
Author(s):  
Duc-Tri Do ◽  
Minh-Khai Nguyen ◽  
Van-Thuyen Ngo ◽  
Thanh-Hai Quach ◽  
Vinh-Thanh Tran
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Space Vector Modulation ◽  
Common Mode ◽  
Switching Sequence ◽  
Modulation Technique ◽  
Common Mode Voltage ◽  
Vector Modulation ◽  
Zero Vector ◽  
Current Ripple

In this paper, the effect of common-mode voltage generated in the three-level quasi-switched boost T-type inverter is minimized by applying the proposed space-vector modulation technique, which uses only medium vectors and zero vector to synthesize the reference vector. The switching sequence is selected smoothly for inserting the shoot-through state for the inverter branch. The shoot-through vector is added within the zero vector in order to not affect the active vectors as well as the output voltage. In addition, the shoot-through control signal of active switches of the impedance network is generated to ensure that its phase is shifted 90 degrees compared to shoot through the signal of the inverter leg, which provides an improvement in reducing the inductor current ripple and enhancing the voltage gain. The effectiveness of the proposed method is verified through simulation and experimental results. In addition, the superiority of the proposed scheme is demonstrated by comparing it to the conventional pulse-width modulation technique.

scholarly journals A Comprehensive AC Current Ripple Analysis and Performance Enhancement via Discontinuous PWM in Three-Phase Four-Leg Grid-Connected Inverters

Energies ◽  
2020 ◽  
Vol 13 (17) ◽  
pp. 4352 ◽  
Author(s):  
Riccardo Mandrioli ◽  
Aleksandr Viatkin ◽  
Manel Hammami ◽  
Mattia Ricco ◽  
Gabriele Grandi
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Performance Enhancement ◽  
Voltage Source ◽  
Complete Analysis ◽  
Switching Frequency ◽  
Output Current ◽  
Voltage Source Inverters ◽  
Switching Losses ◽  
Current Ripple

A complete analysis of the ac output current ripple in four-leg voltage source inverters considering multiple modulation schemes is provided. In detail, current ripple envelopes and peak-to-peak profiles have been determined in the whole fundamental period and a comprehensive method providing the current ripple rms has been achieved, all of them as a function of the modulation index. These characteristics have been determined for both phase and neutral currents, considering the most popular common-mode injection schemes. Particular attention has been paid to the performance of discontinuous pulse width modulation (DPWM) methods, including DPWMMAX and DPWMMIN, and their four most popular combinations DPWM0, DPWM1, DPWM2, and DPWM3. Furthermore, a comparison with a few continuous techniques (sinusoidal, centered pulse width modulations, and third harmonic injection) has been provided as well. Moreover, the average switching frequency and switching losses are analyzed, determining which PWM technique ensures minimum output current ripple within the linear modulation range at different assumptions. Numerical simulations and laboratory tests have been conducted to extensively verify all the analytical claims for all the considered PWM injections.

scholarly journals Algorithim to control output voltage and reduce the ripple of input current in quasi switched boost inverter

2021 ◽  
Vol 4 (2) ◽  
pp. first
Author(s):  
Xuan-Vinh Le ◽  
Duc-Minh Nguyen ◽  
Viet-Anh Truong ◽  
Thanh-Hai Quach
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Short Circuit ◽  
Modulation Index ◽  
Duty Ratio ◽  
Electrical Systems ◽  
Boost Factor ◽  
Control Output ◽  
Current Ripple

In recent years, the quasi -switched boost inverter uses widely in electrical systems. This paper proposes a method to control the AC output voltage and reduce the current ripple of the booster inductor in the quasi-switched boost inverter (QSBI). The proposed technique base on carrier pulse width modulation with two triangles with phase shifts 90◦. This technique uses the offset function to expand the modulation index and the algorithm for output voltage stabilization based on the adjustment of the boost ratio. The modulation index expansion will reduce the stress voltage on the switches by an average of 16.5% under the simulated conditions. The boost factor base on the short circuit time on the DC / DC booster and the inverter on the zero vectors. So, the duty ratio (of the boost DC / DC) can reduce by the short-circuit pulses that insert in the position of zero vectors, so the inverter is responsible for both boosting and inverting. The combination helps to reduce the current ripple on the boost inductor. Besides that, reducing the short-circuit ratio of DC / DC booster will also reduce the capacity of the booster switch and thereby reduce the production cost. The analysis clarifies the proposed technique. Simulations and experiments evaluate the proposed method.

Investigation of Switching Sequences on a Generalized SVPWM Algorithm for Multilevel Inverters

2018 ◽  
Vol 28 (02) ◽  
pp. 1950036 ◽  
Author(s):  
B. Hemanth Kumar ◽  
Makarand M. Lokhande
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Switching Loss ◽  
Voltage Profile ◽  
Switching Sequence ◽  
Multilevel Inverters ◽  
Harmonic Content ◽  
Simulation Results ◽  
Text Location

This paper investigates the various switching sequences on a generalized 60[Formula: see text] distributed coordinate system-based space vector pulse width modulation (SVPWM) algorithm for multilevel inverters. The main focus of this work is to improve the inverter output voltage profile by taking advantage of the redundancy inverter switching states. With the help of SVPWM algorithm, the three nearest vectors have to find out the synthesis of the [Formula: see text] location and then by applying the various optimum switching sequences, the inverter produces less harmonic content in the output voltage compared to the conventional switching sequence. All the switching sequence designs are developed with the help of minimum change detector (MCD) by using switching redundancies in order to reduce inverter switching loss. Simulation results to analyze various sequences on the general SVPWM algorithm are presented in the seven-level cascaded H-bridge (CHB) inverter. To validate the results, hardware results are presented on the seven-level CHB inverter.

scholarly journals Design and implement of pulse width modulation with low-cost hardware in the loop

2020 ◽  
Vol 11 (2) ◽  
pp. 870
Author(s):  
Qasim Al Azze ◽  
Mohammed Hasan Ali
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Low Cost ◽  
Voltage Source ◽  
Hardware In The Loop ◽  
Matlab Simulation ◽  
Output Current ◽  
Voltage Waveform ◽  
Sinusoidal Pulse Width Modulation ◽  
Three Phases

<p>The paper presents a low-cost hardware in the loop based on Arduino. Sinusoidal Pulse Width Modulation (SPWM) designing, analyzing, and implementation is experimented as hardware in the loop. Sinusoidal Pulse Width Modulation implementation via MATLAB\Simulation demonstrates in this work. In this paper, Arduino Mega2560 platform, microcontroller, introduce as hardware. A comparative study of the both techniques is presented. Arduino interfaces with PC Target MATLAB environment. Three phases Voltage Source Inverter directs by the generated pulses that loads with three phases RLC. The obtaining output current and voltage waveform of RLC load of Hardware-in-the-Loop validates to the MATLAB\simulation output waveform. The compering shows the output waveforms are primarily having the same pattern. Arduino consider as the lost cost as microcontroller which could be used in real application.</p>

scholarly journals Novel ripple reduction method using three-level inverters with unipolar PWM

2021 ◽  
Vol 22 (3) ◽  
pp. 1272
Author(s):  
Paiboon Kiatsookkanatorn ◽  
Napat Watjanatepin
Keyword(s):  
Single Phase ◽  
Pulse Width Modulation ◽  
Current Harmonics ◽  
Switching Patterns ◽  
Unipolar Pulse ◽  
Three Phase ◽  
Ripple Reduction ◽  
Novel Method ◽  
Dipolar Modulation ◽  
Current Ripple

This paper proposes a novel method to reduce voltage and current ripple for the inverters by using three-level inverters with unipolar pulse width modulation (PWM) (3LFB-2U). A simple technique of switching signal generation by using carrier-based dipolar modulation of three-phase three-level inverters is extended to single-phase inverters that can be done by generating all possible switching patterns of the single-phase three-level inverters. Moreover, the concept of carrier-based dipolar modulation and the construction of reference voltages from desired output voltage and added zero voltage to control unipolar switching is also shown. The research results reveal that the proposed method can reduce the voltage and current ripple. Furthermore, the voltage and current harmonics can reduce by 27.80% and 1.79%, respectively less than two-level inverters without a loss of a simple modulation to generate the switching signals.

scholarly journals Virtual Space Vector Pulse Width Modulation for Asymmetric T-Type Neutral Point Clamped 3-Level Inverter

2021 ◽  
Vol 2021 ◽  
pp. 1-19
Author(s):  
Nam Xuan Doan ◽  
Nho Van Nguyen
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Low Cost ◽  
Comparative Investigation ◽  
Neutral Point ◽  
Virtual Space ◽  
Vector Diagram ◽  
Space Vector ◽  
Output Performance ◽  
Obvious Benefit

This paper proposes a novel 3-phase asymmetric 3-level T-type NPC inverter and studies its PWM performance using a virtual space vector pulse width modulation control strategy. Firstly, the mathematical model and characteristics of this economical topology are described. Then, a virtual space vector approach is proposed to build a space vector diagram for designing SVPWM control. Similar to the conventional 3-level NPC inverter, the asymmetric inverter can also work with the neutral point voltage self-balancing in a fundamental period, which enables employment of this topology in various applications. Finally, simulation and experiment results under different load conditions have shown good output performance of the asymmetric 3-level topology. Similar tests are also performed on both conventional 2-level and 3-level inverters for comparison. For an almost similar number of different voltage vectors in the space vector diagram, the asymmetric 3-level topology can compete with conventional 3-level inverters for low-cost applications. The obvious benefit of the asymmetric 3-level inverter is a smaller number of switches devices while it can achieve output performance similar to that of the conventional 3-level. The comparative investigation also shows that the total loss given by SVPWM for the asymmetric 3-level configuration is lower than that of the traditional 3-level inverter.

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