scholarly journals Algorithim to control output voltage and reduce the ripple of input current in quasi switched boost inverter

2021 ◽  
Vol 4 (2) ◽  
pp. first
Author(s):  
Xuan-Vinh Le ◽  
Duc-Minh Nguyen ◽  
Viet-Anh Truong ◽  
Thanh-Hai Quach
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Short Circuit ◽  
Modulation Index ◽  
Duty Ratio ◽  
Electrical Systems ◽  
Boost Factor ◽  
Control Output ◽  
Current Ripple

In recent years, the quasi -switched boost inverter uses widely in electrical systems. This paper proposes a method to control the AC output voltage and reduce the current ripple of the booster inductor in the quasi-switched boost inverter (QSBI). The proposed technique base on carrier pulse width modulation with two triangles with phase shifts 90◦. This technique uses the offset function to expand the modulation index and the algorithm for output voltage stabilization based on the adjustment of the boost ratio. The modulation index expansion will reduce the stress voltage on the switches by an average of 16.5% under the simulated conditions. The boost factor base on the short circuit time on the DC / DC booster and the inverter on the zero vectors. So, the duty ratio (of the boost DC / DC) can reduce by the short-circuit pulses that insert in the position of zero vectors, so the inverter is responsible for both boosting and inverting. The combination helps to reduce the current ripple on the boost inductor. Besides that, reducing the short-circuit ratio of DC / DC booster will also reduce the capacity of the booster switch and thereby reduce the production cost. The analysis clarifies the proposed technique. Simulations and experiments evaluate the proposed method.

scholarly journals Single Phase Asymmetrical Cascaded MLI with Extreme Output Voltage Levels to Switch Ratio

2018 ◽  
Vol 9 (2) ◽  
pp. 712
Author(s):  
Mahrous Ahmed ◽  
Essam Hendawi ◽  
Mohamed K. Metwaly
Keyword(s):  
Fundamental Frequency ◽  
Pulse Width ◽  
Output Voltage ◽  
Single Phase ◽  
Pulse Width Modulation ◽  
Modulation Index ◽  
Pwm Control ◽  
Inductive Load ◽  
Control Schemes ◽  
Simulation Results

This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter.

scholarly journals A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs

2020 ◽  
Vol 3 (3) ◽  
pp. first
Author(s):  
Nhờ Văn NGUYỄN ◽  
HONG-PHONG NGUYEN LE
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Short Circuit ◽  
Harmonic Distortion ◽  
Open Circuit ◽  
Neutral Point ◽  
Voltage Source ◽  
Voltage Source Inverters ◽  
Critical Issues

Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.

scholarly journals The Three-Carrier Quasi Switched Boost Inverter Control Technique

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2019
Author(s):  
Thanh-Hai Quach ◽  
Xuan-Vinh Le ◽  
Viet-Anh Truong
Keyword(s):  
Short Circuit ◽  
Conventional Approach ◽  
Experimental Results ◽  
Modulation Index ◽  
Control Technique ◽  
Three Phase ◽  
Calculation Results ◽  
Boost Factor ◽  
Source Voltage ◽  
Current Ripple

This paper presents a carrier modulation technique to control the three-phase, two-level quasi switched boost inverter. This PWM algorithm uses three carrier waves, the first of which is for the inverter while the others are for the booster. The boost factor depends on the short circuit interval on the DC/DC booster and the inverter. When the short circuit interval on the DC boost is twice that on the inverter, the modulation index can be enlarged. The new algorithm is analyzed, calculated, simulated, and tested. The analysis and calculation results show that the proposed technique can reduce the voltage on the DC link capacitor compared to a conventional approach. It can reach 22.16% when the ratio of the DC source voltage to the effective reference voltage is 0.5. The modulation index can extend to 29% under these conditions and the current ripple in the boost inductor can be reduced by 4.8%. The simulation and experimental results also show similarities, thereby confirming the analysis and calculation.

Analysis and simulation of a single-phase seven-level inverter controlled by modified sinusoidal PWM technique

2021 ◽  
pp. 2150024
Author(s):  
V. srinath ◽  
Man Mohan Agarwal ◽  
D. K. Chaturvedi
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Single Phase ◽  
Pulse Width Modulation ◽  
Optimization Technique ◽  
Reference Signal ◽  
Harmonic Distortion ◽  
Modulation Index ◽  
Reference Signals ◽  
Sinusoidal Pulse Width Modulation

In this paper, a modified Sinusoidal Pulse width Modulation (MSPWM) technique and a modified single-phase H-bridge seven-level inverter is proposed. The switching pulses for the proposed seven-level inverter are generated using a single triangular carrier waveform, a fully rectified sinusoidal signal, and three stepped reference signals (Uref1, Uref2 and Uref3). Using optimization technique, the magnitude of the stepped reference signal is determined so that the total harmonic distortion (THD) of the output voltage waveform is minimum and the fundamental component, RMS value of the voltage is improved for a given modulation index Ma as compared to the Sinusoidal Pulse width Modulation (SPWM). By the implementation of the new scheme, the seven-level of the inverter output voltage level (+Vdc, +2Vdc/3, +Vdc/3, 0, −Vdc, −2Vdc/3, −Vdc) is obtained for any given modulation index. Similarly, if only two stepped reference signals are used then the inverter will act as a five-level inverter for any modulating index ma. The proposed MSPWM and seven-level inverter are simulated on MATLAB/SIMULINK for R, R-L load and on a single-phase capacitor-start and capacitor-start-run Induction Motor.

scholarly journals A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2195
Author(s):  
Jin-Wook Kang ◽  
Seung-Wook Hyun ◽  
Yong Kan ◽  
Hoon Lee ◽  
Jung-Hyo Lee
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Dead Time ◽  
Short Circuit ◽  
Reference Voltage ◽  
Voltage Source ◽  
Switching Operation ◽  
Voltage Unbalance ◽  
Offset Voltage ◽  
Simulation And Experiment

This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented.

scholarly journals Research on Modified Hybrid Frequency Modulation Technology of Type-III Asymmetric CHB Multilevel Inverters

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 263
Author(s):  
Manyuan Ye ◽  
Wei Ren ◽  
Qiwen Wei ◽  
Guizhi Song ◽  
Zhilin Miao
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Output Line ◽  
Line Voltage ◽  
Multilevel Inverters ◽  
Type Iii ◽  
Hybrid Frequency ◽  
Frequency Pulse

Asymmetric Cascaded H-bridge (ACHB) level inverters can output more voltage waveforms with fewer cascaded units while ensuring the quality of output voltage waveforms, so they have attracted more and more attention. Taking the topology of Type-III asymmetric CHB multilevel inverters as the research object, a Modified Hybrid Frequency Pulse Width Modulation (MHF-PWM) strategy is proposed in this paper. This modulation strategy overcomes the local overshoot of low-voltage unit in the presence of traditional Hybrid Frequency Pulse Width Modulation (HF-PWM), thus completely eliminating the low frequency harmonics in the output voltage waveform of Type-III ACHB nine-level inverters, and the Total Harmonic Distortion (THD) of output line voltage of the modulation strategy is lower than that of PS-PWM strategy in the whole modulation degree, which effectively improves the quality waveform of the output line voltage. At the same time, the strategy can also improve the problems of current backflow and energy feedback caused by the high-voltage unit pouring current to the low-voltage unit, thereby reducing the imbalance of the output power of the high-voltage and low-voltage units. Finally, the Matlab/Simulink simulation model and experimental platform are established to verify the validity and practicality of the modulation strategy.

Designing of a High Voltage Power Supply for Electrospinning Apparatus Using a High Voltage Flyback Transformer (HVFBT)

2015 ◽  
Vol 771 ◽  
pp. 145-148 ◽  
Author(s):  
Muhammad Miftahul Munir ◽  
Dian Ahmad Hapidin ◽  
Khairurrijal
Keyword(s):  
High Voltage ◽  
Duty Cycle ◽  
Power Supply ◽  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Experimental Results ◽  
High Voltage Power Supply ◽  
Electrospinning Technique ◽  
The World

Research on nanofiber materials is actively done around the world today. Various types of nanofibers have been synthesized using an electrospinning technique. The most important component when synthesizing nanofibers using the electrospinning technique is a DC high voltage power supply. Some requirements must be fulfilled by the high voltage power supply, i.e., it must be adjustable and its output voltage reaches tens of kilovolts. This paper discusses the design and development of a high voltage power supply using a diode-split transformer (DST)-type high voltage flyback transformer (HVFBT). The DST HVFBT was chosen because of its simplicity, compactness, inexpensiveness, and easiness of finding it. A pulse-width modulation (PWM) circuit with controlling frequency and duty cycle was fed to the DST HVFBT. The high voltage power supply was characterized by the frequency and duty cycle dependences of its output voltage. Experimental results showed that the frequency and duty cycle affect the output voltage. The output voltage could be set from 1 to 18 kV by changing the duty cycle. Therefore, the nanofibers could be synthesized by employing the developed high voltage power supply.

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