A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.

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A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078720001087 ◽

2020 ◽

pp. 1-18

Author(s):

Florent Torres ◽

Eric Kerhervé ◽

Andreia Cathelin ◽

Magali De Matos

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Fully Depleted ◽

Technology Roadmap ◽

Wide Range ◽

28 Nm ◽

Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

Electronics ◽

10.3390/electronics9040580 ◽

2020 ◽

Vol 9 (4) ◽

pp. 580

Author(s):

Peng Cao ◽

Wei Bao ◽

Jingjing Guo

Keyword(s):

Circuit Design ◽

Supply Voltage ◽

Timing Analysis ◽

Instruction Set ◽

Timing Verification ◽

Static Timing Analysis ◽

Static Timing ◽

Threshold Voltages ◽

Layer Stacking ◽

Reduced Instruction Set Computer

The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

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Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology

Journal of Low Power Electronics ◽

10.1166/jolpe.2016.1421 ◽

2016 ◽

Vol 12 (1) ◽

pp. 64-73 ◽

Cited By ~ 5

Author(s):

Zhaopeng Wei ◽

Gilles Jacquemod ◽

Philippe Lorenzini ◽

Frederic Hameau ◽

Emeric de Foucauld ◽

...

Keyword(s):

Silicon On Insulator ◽

Fully Depleted ◽

Silicon On Insulator Technology ◽

28 Nm

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Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices

Journal of Low Power Electronics ◽

10.1166/jolpe.2016.1420 ◽

2016 ◽

Vol 12 (1) ◽

pp. 58-63

Author(s):

Rida Kheirallah ◽

Gilles Ducharme ◽

Nadine Azemard

Keyword(s):

Silicon On Insulator ◽

Fully Depleted ◽

28 Nm

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Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

Solid-State Electronics ◽

10.1016/j.sse.2015.11.006 ◽

2016 ◽

Vol 117 ◽

pp. 37-59 ◽

Cited By ~ 12

Author(s):

B. Doris ◽

B. DeSalvo ◽

K. Cheng ◽

P. Morin ◽

M. Vinet

Keyword(s):

Silicon On Insulator ◽

Fully Depleted ◽

28 Nm

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High-Speed Serializer for a 64 GS s<sup>−1</sup> Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

Advances in Radio Science ◽

10.5194/ars-16-99-2018 ◽

2018 ◽

Vol 16 ◽

pp. 99-108

Author(s):

Daniel Widmann ◽

Markus Grözing ◽

Manfred Berroth

Keyword(s):

High Speed ◽

Average Power ◽

Silicon On Insulator ◽

Output Stage ◽

Fully Depleted ◽

Data Rates ◽

Average Power Consumption ◽

Digital To Analog ◽

On Chip ◽

28 Nm

Abstract. An attractive solution to provide several channels with very high data rates of tens of Gbit s−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit s−1 per channel and a low skew (∼ 8.8 ps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 bit 64 GS s−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 ps at the output of one MUX channel with a total average power consumption of approximately 1.15 W of the whole MUX and clock network.

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High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea10030027 ◽

2020 ◽

Vol 10 (3) ◽

pp. 27

Author(s):

Andrea Ballo ◽

Alfio Dario Grasso ◽

Salvatore Pennisi ◽

Chiara Venezia

Keyword(s):

Resonant Frequency ◽

Performance Optimization ◽

Cmos Technology ◽

Second Order ◽

Silicon On Insulator ◽

Circuit Performance ◽

Fully Depleted ◽

Current Consumption ◽

28 Nm ◽

Soi Cmos

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

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