1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

Indium Lead Oxide (ILO) based Metal Oxide Thin Film Transistor (MOTFT) is fabricated with Lead Barium Zirconate (PBZ) gate dielectric. PBZ is formed over doped silicon substrate by cheap sol-gel process. Thin film PBZ is analysed with X-ray Diffraction (XRD), Ultra-Violet Visible Spectra (UV-Vis) and Atomic Force Microscope (AFM). IZO is used as bottom gate to contact Thin Film Transistor (TFT). This device needs only 5V as operating voltage, and so is good for lower electronics <40V. It shows excellent emobility 4.5cm2/V/s, with on/off ratio 5×105 and sub-threshold swing 0.35V/decade.

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Influence of Active Channel Layer Thickness on SnO2 Thin-Film Transistor Performance

Electronics ◽

10.3390/electronics10020200 ◽

2021 ◽

Vol 10 (2) ◽

pp. 200

Author(s):

Do Won Kim ◽

Hyeon Joong Kim ◽

Changmin Lee ◽

Kyoungdu Kim ◽

Jin-Hyuk Bae ◽

...

Keyword(s):

Thin Film ◽

Field Effect ◽

Thin Film Transistor ◽

Sol Gel ◽

Precursor Concentration ◽

Sno2 Thin Film ◽

Field Effect Mobility ◽

Si Substrates ◽

Channel Layer ◽

Active Channel

Sol-gel processed SnO2 thin-film transistors (TFTs) were fabricated on SiO2/p+ Si substrates. The SnO2 active channel layer was deposited by the sol-gel spin coating method. Precursor concentration influenced the film thickness and surface roughness. As the concentration of the precursor was increased, the deposited films were thicker and smoother. The device performance was influenced by the thickness and roughness of the SnO2 active channel layer. Decreased precursor concentration resulted in a fabricated device with lower field-effect mobility, larger subthreshold swing (SS), and increased threshold voltage (Vth), originating from the lower free carrier concentration and increase in trap sites. The fabricated SnO2 TFTs, with an optimized 0.030 M precursor, had a field-effect mobility of 9.38 cm2/Vs, an SS of 1.99, an Ion/Ioff value of ~4.0 × 107, and showed enhancement mode operation and positive Vth, equal to 9.83 V.

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Performance Improvement of ZnSnO Thin-Film Transistors with Low-Temperature Self-Combustion Reaction

Electronics ◽

10.3390/electronics10091099 ◽

2021 ◽

Vol 10 (9) ◽

pp. 1099

Author(s):

Ye-Ji Han ◽

Se Hyeong Lee ◽

So-Young Bak ◽

Tae-Hee Han ◽

Sangwoo Kim ◽

...

Keyword(s):

Thin Film ◽

Photoelectron Spectroscopy ◽

Large Scale ◽

Low Cost ◽

Thermal Analyses ◽

Thin Film Transistor ◽

Sol Gel ◽

Annealing Temperatures ◽

Zinc Tin Oxide ◽

Thermal Limitation

Conventional sol-gel solutions have received significant attention in thin-film transistor (TFT) manufacturing because of their advantages such as simple processing, large-scale applicability, and low cost. However, conventional sol-gel processed zinc tin oxide (ZTO) TFTs have a thermal limitation in that they require high annealing temperatures of more than 500 °C, which are incompatible with most flexible plastic substrates. In this study, to overcome the thermal limitation of conventional sol-gel processed ZTO TFTs, we demonstrated a ZTO TFT that was fabricated at low annealing temperatures of 350 °C using self-combustion. The optimized device exhibited satisfactory performance, with μsat of 4.72 cm2/V∙s, Vth of −1.28 V, SS of 0.86 V/decade, and ION/OFF of 1.70 × 106 at a low annealing temperature of 350 °C for one hour. To compare a conventional sol-gel processed ZTO TFT with the optimized device, thermogravimetric and differential thermal analyses (TG-DTA) and X-ray photoelectron spectroscopy (XPS) were implemented.

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Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

VNU Journal of Science Mathematics - Physics ◽

10.25073/2588-1124/vnumap.4351 ◽

2019 ◽

Vol 35 (2) ◽

Author(s):

Bui Nguyen Quoc Trinh

Keyword(s):

Thin Film ◽

Thin Film Transistor ◽

Sol Gel ◽

Gate Insulator ◽

Current Ratio ◽

Memory State ◽

Small Loss ◽

Memory Circuit ◽

Novel Concept ◽

Data Reading

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle. Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

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