scholarly journals Anisotropic Grain Growth in (111) Nanotwinned Cu Films by DC Electrodeposition

Materials ◽  
2019 ◽  
Vol 13 (1) ◽  
pp. 134 ◽  
Author(s):  
Tien-Lin Lu ◽  
Yu-An Shen ◽  
John A. Wu ◽  
Chih Chen
Keyword(s):  
Grain Growth ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
X Ray ◽  
Cu Films ◽  
3D Ic Packaging ◽  
Cu Film ◽  
Average Grain Size ◽  
Three Dimensional Integrated Circuit ◽  
Grain Growth Behavior

We have reported a method of fabricating (111)-orientated nanotwinned copper (nt-Cu) by direct current electroplating. X-ray analysis was performed for the samples annealed at 200 to 350 °C for an hour. X-ray diffraction indicates that the (200) signal intensity increases while (111) decreases. Abnormal grain growth normally results from transformation of surface energy or strain energy density. The average grain size increased from 3.8 µm for the as-deposited Cu films to 65–70 µm after the annealing at 250 °C for 1 h. For comparison, no significant grain growth behavior was observed by random Cu film after annealing for an hour. This research shows the potential for its broad electric application in interconnects and three-dimensional integrated circuit (3D IC) packaging.

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

2014 ◽  
Vol 136 (4) ◽  
Author(s):  
John H. Lau
Keyword(s):  
Integrated Circuit ◽  
State Of The Art ◽  
Three Dimensional ◽  
High Volume ◽  
3D Integration ◽  
3D Ic ◽  
3D Ic Packaging ◽  
Ic Packaging ◽  
Circuit Integration ◽  
Three Dimensional Integrated Circuit

3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.

Study of Bonded Wafers by Using a Synchrotron Radiation Transmission X-ray Microscopy for Three-Dimensional Integrated Circuit

2020 ◽  
Vol 15 (7) ◽  
pp. 904-908
Author(s):  
Youn-Jang Kim ◽  
Jae-Hong Lim ◽  
Kyeong-Keun Choi
Keyword(s):  
Synchrotron Radiation ◽  
Integrated Circuit ◽  
Interfacial Layer ◽  
Three Dimensional ◽  
Experimental Results ◽  
X Ray ◽  
Radiation Transmission ◽  
Three Dimensional Integrated Circuit

Synchrotron radiation transmission X-ray microscopy (SRTXM) was applied for visualization of the interfacial layer in bonded wafer pairs. The X-ray energy of 6.54 keV with a monitoring window was utilized to enhance a resolution of transmission X-ray microscopy (TXM). The monitoring window was designed a locally uncovered area of the bonded wafer pairs to make the thickness of bonded wafers less than 200 μm. The experimental results showed that the technique has sub-micron meter resolution. Also this technique can improve the resolution of the synchrotron X-ray for nanoelectronics application.

Effect of Film Thickness on the Annealing Texture in Sputtered and Electroplated Cu Films

2006 ◽  
Vol 15-17 ◽  
pp. 982-988
Author(s):  
Sang Hoon Lee ◽  
No Jin Park ◽  
David P. Field ◽  
Paul R. Besser
Keyword(s):  
Film Thickness ◽  
Grain Growth ◽  
Processing Conditions ◽  
X Ray ◽  
Cu Films ◽  
Annealing Texture ◽  
Cu Film ◽  
The Relationship ◽  
Si Wafer

For optimum fabrication and usage of Cu films, an understanding of the relationship between processing and microstructure is required. The existence of twins is another significant factor for texture development in Cu films. Texture character and strength in the Cu film is dependent on the twin boundary development that is a function of processing conditions and film thickness. In this study, determination of grain growth and texture in the sputtered and electroplated Cu films during annealing was performed for films of 100, 480 and 850 nm in thickness deposited on a Ta(25 nm)/Si wafer. The texture was measured by X-ray pole figure. The effect of film thickness on the annealing texture in the sputtered and electroplated Cu films is examined and discussed.

Relaxation and Grain Growth Behavior of Nanocrystalline Iron

1992 ◽  
Vol 272 ◽  
Author(s):  
J. C. Holzer ◽  
R. Birringer ◽  
J. Eckert ◽  
C.E. Krill ◽  
W.L. Johnson
Keyword(s):  
Grain Size ◽  
Grain Growth ◽  
Scanning Calorimetry ◽  
X Ray ◽  
Peak Broadening ◽  
Transmission Electron ◽  
Average Grain Size ◽  
Nanocrystalline Iron ◽  
Grain Growth Behavior ◽  
Kinetics Of

ABSTRACTNanocrystalline Fe has been prepared by inert gas condensation and ball milling. The kinetics of relaxation and grain growth are investigated by differential scanning calorimetry. The development of the microstructure is monitored by x-ray powder diffraction and transmission electron microscopy. Emphasis is placed on the differences observed for samples prepared by the two different techniques. We find that the kinetics of relaxation and grain growth are very sensitive to the sample preparation method. Samples with the same initial average grain size, as determined by the peak broadening in x-ray diffraction, show very different recovery behavior. The differences are discussed in terms of the estimated grain boundary energies and the initial grain size distribution obtained by the two preparation techniques.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

The Microstructure and Electrical Property of Porous Cu Film on Soft PVDF Substrate

2012 ◽  
Vol 472-475 ◽  
pp. 1451-1454
Author(s):  
Xue Hui Wang ◽  
Wu Tang ◽  
Ji Jun Yang
Keyword(s):  
Electrical Properties ◽  
Film Surface ◽  
X Ray Diffraction ◽  
Si Substrate ◽  
X Ray ◽  
Cu Films ◽  
Cu Film ◽  
Diffraction Peaks ◽  
Sputtering Pressure ◽  
Effect Method

The porous Cu film was deposited on soft PVDF substrate by magnetron sputtering at different sputtering pressure. The microstructure and electrical properties of Cu films were investigated as a function of sputtering pressure by X-ray diffraction XRD and Hall effect method. The results show that the surface morphology of Cu film is porous, and the XRD revealed that there are Cu diffraction peaks with highly textured having a Cu-(220) or a mixture of Cu-(111) and Cu-(220) at sputtering pressure 0.5 Pa. The electrical properties are also severely influenced by sputtering pressure, the resistivity of the porous Cu film is much larger than that fabricated on Si substrate. Furthermore, the resistivity increases simultaneously with the increasing of Cu film surface aperture, but the resistivity of Cu film still decreases with the increasing grain size. It can be concluded that the crystal structure is still the most important factor for the porous Cu film resistivity.

Stress development and relaxation in copper films during thermal cycling

1993 ◽  
Vol 8 (8) ◽  
pp. 1845-1852 ◽  
Author(s):  
M.D. Thouless ◽  
J. Gupta ◽  
J.M.E. Harper
Keyword(s):  
Thermal Cycling ◽  
Integrated Circuit ◽  
Temperature Hysteresis ◽  
Copper Films ◽  
Cu Films ◽  
Dislocation Glide ◽  
Temperature Range ◽  
Cu Film ◽  
Relaxation Of Stresses ◽  
Power Law Creep

The reliability of integrated-circuit wiring depends strongly on the development and relaxation of stresses that promote void and hillock formation. In this paper an analysis based on existing models of creep is presented that predicts the stresses developed in thin blanket films of copper on Si wafers subjected to thermal cycling. The results are portrayed on deformation-mechanism maps that identify the dominant mechanisms expected to operate during thermal cycling. These predictions are compared with temperature-ramped and isothermal stress measurements for a 1 μm-thick sputtered Cu film in the temperature range 25–450 °C. The models successfully predict both the rate of stress relaxation when the film is held at a constant temperature and the stress-temperature hysteresis generated during thermal cycling. For 1 μm-thick Cu films cycled in the temperature range 25–450 °C, the deformation maps indicate that grain-boundary diffusion controls the stress relief at higher temperatures (>300 °C) when only a low stress can be sustained in the films, power-law creep is important at intermediate temperatures and determines the maximum compressive stress, and that if yield by dislocation glide (low-temperature plasticity) occurs, it will do so only at the lowest temperatures (<100 °C). This last mechanism did not appear to be operating in the film studied for this project.

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