scholarly journals A 45 nm CMOS Avalanche Photodiode with 8.4-GHz Bandwidth

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 65
Author(s):  
Wenhao Zhi ◽  
Qingxiao Quan ◽  
Pingping Yu ◽  
Yanfeng Jiang
Keyword(s):  
Optical Communication ◽  
Integrated Circuit ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Avalanche Photodiode ◽  
Cmos Technology ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Monolithically Integrated ◽  
Process Modification

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.

scholarly journals Integrated silicon carbide modulator for CMOS photonics

2021 ◽  
Author(s):  
Keith Powell ◽  
Liwei Li ◽  
Amirhassan Shams-Ansari ◽  
Jianfu Wang ◽  
Debin Meng ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Oxide Semiconductor ◽  
Photon Absorption ◽  
Stable Operation ◽  
Pockels Effect ◽  
Long Distance ◽  
Optical Carrier

Abstract The electro-optic modulator encodes electrical signals onto an optical carrier, and is essential for the operation of global communication systems and data centers that society demands. An ideal modulator results from scalable semiconductor fabrication and is integrable with electronics. Accordingly, it is compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes. Moreover, modulators using the Pockels effect enables low loss, ultrafast, and wide-bandwidth data transmission. Although strained silicon-based modulators could satisfy these criteria, fundamental limitations such as two-photon absorption, poor thermal stability and a narrow transparency window hinder their performance. On the other hand, as a wide bandgap semiconductor material, silicon carbide is CMOS compatible and does not suffer from these limitations. Due to its combination of color centers, high breakdown voltage, and strong thermal conductivity, silicon carbide is a promising material for CMOS electronics and photonics with applications ranging from sensors to quantum and nonlinear photonics. Importantly, silicon carbide exhibits the Pockels effect, but a modulator has not been realized since the discovery of this effect more than three decades ago. Here we design, fabricate, and demonstrate the first Pockels modulator in silicon carbide. Specifically, we realize a waveguide-integrated, small form-factor, gigahertz-bandwidth modulator that can operate using CMOS-level drive voltages on a thin film of silicon carbide on insulator. Furthermore, the device features no signal degradation and stable operation at high optical intensities (913 kW/mm2), allowing for high optical signal-to-noise ratios for long distance communications. Our work unites Pockels electro-optics with a CMOS platform to pave the way for foundry-compatible integrated photonics.

scholarly journals Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

Nanophotonics ◽  
2017 ◽  
Vol 6 (6) ◽  
pp. 1343-1352 ◽  
Author(s):  
Chuantong Cheng ◽  
Beiju Huang ◽  
Xurui Mao ◽  
Zanyun Zhang ◽  
Zan Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Three Dimensional ◽  
Complementary Metal Oxide Semiconductor ◽  
Optical Signal ◽  
Optical Interconnect ◽  
Optical Receiver ◽  
Oxide Semiconductor ◽  
Experimental Realization ◽  
Operation Speed

AbstractOptical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

scholarly journals Design and Characteristics of CMOS Inverter based on Multisim and Cadence

2021 ◽  
Vol 2108 (1) ◽  
pp. 012034
Author(s):  
Haoran Xu ◽  
Jianghua Ding ◽  
Jian Dang
Keyword(s):  
Metal Oxide ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Data Converters ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
And Performance

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

scholarly journals LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2010
Author(s):  
Chen-Hung Lin ◽  
Chen-Xuan Wang ◽  
Cheng-Kai Lu
Keyword(s):  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Compensation Scheme ◽  
Dual Mode ◽  
Ldpc Decoder ◽  
Performance Loss ◽  
Ldpc Decoding ◽  
5G Communication

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.

scholarly journals An Interface ASIC for MEMS Vibratory Gyroscopes with Nonlinear Driving Control

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 270 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Liang Yin ◽  
Yuan Gao ◽  
Wei Bai ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Resonance Oscillation ◽  
Temperature Drift ◽  
Sigma Delta ◽  
Vibratory Gyroscopes ◽  
Digital Circuitry ◽  
Mems Vibratory Gyroscopes

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Layout Design ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sensor Applications

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

scholarly journals A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

2017 ◽  
Vol 7 (1) ◽  
Author(s):  
B. Chakrabarti ◽  
M. A. Lastras-Montaño ◽  
G. Adam ◽  
M. Prezioso ◽  
B. Hoskins ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Switching Behavior ◽  
Molecular Architecture ◽  
Monolithically Integrated ◽  
Computing Paradigm ◽  
Memristor Crossbar ◽  
2D And 3D ◽  
Hybrid Circuit

Abstract Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

scholarly journals High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 579 ◽  
Author(s):  
Martín Riverola ◽  
Francesc Torres ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Life Time ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Mechanical Contact ◽  
Contact Materials ◽  
Monolithically Integrated ◽  
Cmos Mems ◽  
Mechanical Logic

In this paper, a seesaw torsional relay monolithically integrated in a standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology is presented. The seesaw relay is fabricated using the Back-End-Of-Line (BEOL) layers available, specifically using the tungsten VIA3 layer of a 0.35 μm CMOS technology. Three different contact materials are studied to discriminate which is the most adequate as a mechanical relay. The robustness of the relay is proved, and its main characteristics as a relay for the three different contact interfaces are provided. The seesaw relay is capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. The low contact resistance achieved with the TiN/W mechanical contact with high cycling life time is competitive in comparison with the state-of-the art.

scholarly journals A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5303
Author(s):  
Yongho Lee ◽  
Shinil Chang ◽  
Jungah Kim ◽  
Hyunchol Shin
Keyword(s):  
Integrated Circuit ◽  
Communication Systems ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Noise ◽  
Second Order ◽  
The Body ◽  
Oxide Semiconductor ◽  
Biomedical Devices ◽  
Passive Mixer ◽  
Rf Receiver

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands.

Sign in / Sign up

Export Citation Format

Share Document