scholarly journals Research of Wafer Level Bonding Process Based on Cu–Sn Eutectic

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 789
Author(s):  
Daowei Wu ◽  
Wenchao Tian ◽  
Chuqiao Wang ◽  
Ruixia Huo ◽  
Yongkun Wang
Keyword(s):  
Oxide Layer ◽  
Performance Indicators ◽  
Metal Layer ◽  
Bonding Process ◽  
Wafer Surface ◽  
Wafer Level ◽  
Industry Standards ◽  
Vertical Interconnection ◽  
Pretreatment Conditions ◽  
System Packaging

In 3D-system packaging technologies, eutectic bonding is the key technology of multilayer chip stacking and vertical interconnection. Optimized from the aspects of the thickness of the electroplated metal layer, the pretreatment of the wafer surface removes the oxide layer, the mutual alignment between the wafers, the temperature of the wafer bonding, the uniformity of pressure and the deviation of the bonding process. Under the pretreatment conditions of plasma treatment and citric acid cleaning, no oxide layer was obtained on the metal surface. Cu/Sn bumps bonded under the condition of 0.135 Mpa, temperature of 280 °C, Sn thickness of 3–4 μm and a Cu-thickness of five micrometers. Bonded push crystal strength ≥18 kg/cm2, the average contact resistance of the bonding interface is about 3.35 mΩ, and the bonding yield is 100%. All performance indicators meet and exceed the industry standards.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Characterization of Wafer Level Metal Thermo-Compression Bonding

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002326-002360
Author(s):  
Erkan Cakmak ◽  
Bioh Kim ◽  
Viorel Dragoi
Keyword(s):  
Surface Treatment ◽  
Metal Surface ◽  
Bonding Temperature ◽  
Transient Liquid Phase ◽  
Bonding Process ◽  
Bending Test ◽  
Strength Analysis ◽  
Mems Devices ◽  
Wafer Level ◽  
Bond Quality

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB. In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test. Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system. To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.

Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001555-001595
Author(s):  
Cornelia Tsang ◽  
Janet Okada ◽  
Eric Huenger
Keyword(s):  
Printed Circuit Boards ◽  
Process Integration ◽  
Product Yield ◽  
Wafer Surface ◽  
Wafer Level ◽  
Design Elements ◽  
Conformal Coating ◽  
3D Packaging ◽  
Study Process ◽  
Negative Tone

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions. In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths. This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Reliability and Characterization of Micro-Packages in a Wafer Level Au-Si Eutectic Vacuum Bonding Process

2005 ◽  
Author(s):  
Jay S. Mitchell ◽  
Gholamhassan R. Lahiji ◽  
Khalil Najafi
Keyword(s):  
High Sensitivity ◽  
Pressure Change ◽  
Bonding Process ◽  
Wafer Level ◽  
Eutectic Solder ◽  
Packaging Process ◽  
Primary Mechanism ◽  
Airtight Seal ◽  
Over Time

A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of devices was achieved by bonding a silicon cap wafer to a device wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of <10 mTorr/year. Trends in pressure over time seem to indicate outgassing (desorption of atoms from inside of the microcavity) as the primary mechanism for pressure change over time.

Metal Etch in Advanced Immersion Tank with Precision Uniformity Using Agitation and Wafer Rotation

2014 ◽  
Vol 219 ◽  
pp. 138-142
Author(s):  
Scott Tice ◽  
Chan Geun Park
Keyword(s):  
Metal Layer ◽  
Electrical Potential ◽  
Dry Etching ◽  
Metal Films ◽  
Wafer Fabrication ◽  
Wafer Surface ◽  
Semiconductor Wafer ◽  
Isotropic Etching ◽  
Semiconductor Wafer Fabrication ◽  
Metal Etching

In semiconductor wafer fabrication, etching refers to the process of removing unwanted material from wafer surface through a subtractive process. Metal etching is most commonly used in the patterning of metal films for interconnects by establishing specific connection and conduction paths and can be classified by dry etching, de-plating and dissolution of the layers on various substrates such as silicon, SiO2, Si3N4, GaAs, germanium, and sapphire. Dry etching is used to produce very precise etching of vertical channels or vias forming the device features or lines which make up the conductive path because it is anisotropic or etching in one direction. Dry etching is achieved by using chemical gases and plasma in a process chamber so dry etching tools are very large, complex and expensive to purchase and operate. De-plating is a process of electro-chemically removing metal material from the surface of the wafer to an anode by creating a difference in electrical potential between the surface to be etched/de-plated (typically cathode) and the “target” or anode where the material is to be collected. De-plating in single wafer tools has also replaced immersion processing due to the better uniformity it provides. However, De-plating single wafer tools are also very large and expensive to operate and have low throughput (wafers per hour). Dissolution/Immersion is the used of recirculated chemical baths to perform the etching process. In an immersion bath chemical is used to dissolve the metal layer that is unprotected by the mask. Immersion metal etch process has been on the decline because of its isotropic etching property and poor etch uniformity caused by non-uniform chemical flow around wafers in the tank. For the most of etch processes lateral etching is undesired because it occurs on the walls of the features and makes them thinner or misshapen. As a result, most of critical etching steps are performed by dry etching systems. However, if etch uniformity is precise, immersion etching can be used for less critical features in place of complex dry etching and de-plating.

Development of Titanium-Calcium Alloy Resistant to Aqueous Fluoride Solutions

2010 ◽  
Vol 638-642 ◽  
pp. 564-569 ◽  
Author(s):  
Takumi Haruna ◽  
Itsuki Shinohara
Keyword(s):  
Stainless Steel ◽  
Corrosion Resistance ◽  
Oxide Layer ◽  
Metal Layer ◽  
Holding Time ◽  
The Other ◽  
Fluoride Ion ◽  
Micro Hardness ◽  
Immersion Condition ◽  
Vickers Micro Hardness

It has been tried to develop Ti-Ca alloys which demonstrates corrosion resistance in an aqueous fluoride solutions. The Ti-Ca alloys were produced by diffusion-metallizing method. A Ti plate and Ca grains were put in a sealed container of stainless steel. As the container was heated at 1000 oC, Ca was melted and partially vaporized in the inner space. Ca then contacts and permeats into the Ti plate to metallize. In a holding time of 450 h, the alloy surface consisted of two layers, the first was oxide layer and the second was metal layer of about 200 m thick. A Vickers micro hardness of the second layer was quite large, upto about 600 Hv. Evaluation of corrosion resistance for the second layer and the inner part was carried out by electrochemical potentiokinetic method. Test solutions were aqueous fluoride solutions produced with HF and NaF. A concentration of fluoride ion was fixed to 0.024 kmol m-3, and pH of the solution was varied from 3.4 to 4.7. As a result, both Ti and Ti-Ca alloy were passivated under natural immersion condition in the solution of pH 4.7. At pH 3.4, on the other hand, Ti was actively dissolved, but Ti-Ca alloy was still passivated, that means Ti-Ca alloy performs much better corrosion resistance than Ti.

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