scholarly journals Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1155
Author(s):  
Woojin Park ◽  
Yusin Pak ◽  
Hye Yeon Jang ◽  
Jae Hyeon Nam ◽  
Tae Hyeon Kim ◽  
...  

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Nanoscale ◽  
2020 ◽  
Vol 12 (16) ◽  
pp. 8883-8889 ◽  
Author(s):  
Ronen Dagan ◽  
Yonatan Vaknin ◽  
Yossi Rosenwaks

Gap states and Fermi level pinning play an important role in all semiconductor devices, but even more in transition metal dichalcogenide-based devices due to their high surface to volume ratio and the absence of intralayer dangling bonds.


2021 ◽  
pp. 2001212
Author(s):  
Tien Dat Ngo ◽  
Zheng Yang ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Inyong Moon ◽  
...  

Author(s):  
Tien Dat Ngo ◽  
Min Sup Choi ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Won Jong Yoo

A technique to form the edge contact in two-dimensional (2D) based field-effect transistors (FETs) has been intensively studied for the purpose of achieving high mobility and also recently overcoming the...


2020 ◽  
Vol 8 (1) ◽  
pp. 201-208 ◽  
Author(s):  
Taikyu Kim ◽  
Jeong-Kyu Kim ◽  
Baekeun Yoo ◽  
Hongwei Xu ◽  
Sungyeon Yim ◽  
...  

Metal–interlayer–semiconductor contact reduces metal-induced gap states, mitigating Fermi-level pinning at metal/semiconductor interface. Here, switching property of p-type SnO FET is enhanced by increasing electron Schottky barrier at off-state.


2019 ◽  
Vol 9 (23) ◽  
pp. 5014
Author(s):  
Courtin ◽  
Moréac ◽  
Delhaye ◽  
Lépine ◽  
Tricot ◽  
...  

Fermi level pinning at metal/semiconductor interfaces forbids a total control over the Schottky barrier height. 2D materials may be an interesting route to circumvent this problem. As they weakly interact with their substrate through Van der Waals forces, deposition of 2D materials avoids the formation of the large density of state at the semiconductor interface often responsible for Fermi level pinning. Here, we demonstrate the possibility to alleviate Fermi-level pinning and reduce the Schottky barrier height by the association of surface passivation of germanium with the deposition of 2D graphene.


2020 ◽  
Vol 10 (8) ◽  
pp. 2754
Author(s):  
Yu Zhang ◽  
Xiong Chen ◽  
Hao Zhang ◽  
Xicheng Wei ◽  
Xiangfeng Guan ◽  
...  

Molybdenum disulfide (MoS2) field-effect transistors (FETs) with four different metallic electrodes (Au,Ag,Al,Cu) of drain-source were fabricated by mechanical exfoliation and vacuum evaporation methods. The mobilities of the devices were (Au) 21.01, (Ag) 23.15, (Al) 5.35 and (Cu) 40.52 cm2/Vs, respectively. Unpredictably, the on-state currents of four devices were of the same order of magnitude with no obvious difference. For clarifying this phenomenon, we calculated the Schottky barrier height (SBH) of the four metal–semiconductor contacts by thermionic emission theory and confirmed the existence of Fermi-level pinning (FLP). We suppose the FLP may be caused by surface states of the semiconductor produced from crystal defects.


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