Improved switching characteristics of p-type tin monoxide field-effect transistors through Schottky energy barrier engineering

2020 ◽  
Vol 8 (1) ◽  
pp. 201-208 ◽  
Author(s):  
Taikyu Kim ◽  
Jeong-Kyu Kim ◽  
Baekeun Yoo ◽  
Hongwei Xu ◽  
Sungyeon Yim ◽  
...  
Keyword(s):  
Energy Barrier ◽  
Field Effect Transistors ◽  
Semiconductor Interface ◽  
Fermi Level Pinning ◽  
Switching Property ◽  
Switching Characteristics ◽  
Gap States ◽  
P Type ◽  
Tin Monoxide ◽  
Semiconductor Contact

Metal–interlayer–semiconductor contact reduces metal-induced gap states, mitigating Fermi-level pinning at metal/semiconductor interface. Here, switching property of p-type SnO FET is enhanced by increasing electron Schottky barrier at off-state.

Anomalously persistent p-type behavior of WSe2 field-effect transistors by oxidized edge-induced Fermi-level pinning

2022 ◽  
Author(s):  
Tien Dat Ngo ◽  
Min Sup Choi ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Won Jong Yoo
Keyword(s):  
Fermi Level ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Mobility ◽  
Two Dimensional ◽  
Edge Contact ◽  
Fermi Level Pinning ◽  
P Type

A technique to form the edge contact in two-dimensional (2D) based field-effect transistors (FETs) has been intensively studied for the purpose of achieving high mobility and also recently overcoming the...

Gap state distribution and Fermi level pinning in monolayer to multilayer MoS2 field effect transistors

Nanoscale ◽  
2020 ◽  
Vol 12 (16) ◽  
pp. 8883-8889 ◽  
Author(s):  
Ronen Dagan ◽  
Yonatan Vaknin ◽  
Yossi Rosenwaks
Keyword(s):  
Transition Metal ◽  
Fermi Level ◽  
Field Effect ◽  
Field Effect Transistors ◽  
High Surface ◽  
Volume Ratio ◽  
Transition Metal Dichalcogenide ◽  
State Distribution ◽  
Fermi Level Pinning ◽  
Gap States

Gap states and Fermi level pinning play an important role in all semiconductor devices, but even more in transition metal dichalcogenide-based devices due to their high surface to volume ratio and the absence of intralayer dangling bonds.

scholarly journals Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1155
Author(s):  
Woojin Park ◽  
Yusin Pak ◽  
Hye Yeon Jang ◽  
Jae Hyeon Nam ◽  
Tae Hyeon Kim ◽  
...  
Keyword(s):  
Fermi Level ◽  
Interfacial Layer ◽  
High Performance ◽  
Field Effect Transistors ◽  
Transition Metal Dichalcogenide ◽  
Tio2 Layer ◽  
Semiconductor Interface ◽  
Fermi Level Pinning ◽  
Bias Stress ◽  
Voltage Variation

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Source and Drain Contacts for Germanium and III–V FETs for Digital Logic

MRS Bulletin ◽  
2009 ◽  
Vol 34 (7) ◽  
pp. 522-529 ◽  
Author(s):  
Athanasios Dimoulas ◽  
Akira Toriumi ◽  
Suzanne E. Mohney
Keyword(s):  
Field Effect ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Digital Logic ◽  
Semiconductor Interface ◽  
Fermi Level Pinning ◽  
Specific Contact ◽  
Effect Transistor ◽  
The Many

AbstractThe scaling of transistors to smaller dimensions and the exploration of devices with III–V and Ge channels for digital logic places serious demands on the ohmic contacts used in these devices. Contacts with extremely low specific contact resistances are required to take full advantage of the performance promised by alternative semiconductor materials. In addition, device processes and contact morphologies must be compatible with the geometry and feature sizes of the transistors. In this article, we begin by reviewing what is known about contacts to Ge, InGaAs, InAs, and InSb, including the role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts. Then we turn our attention to the additional challenges faced when preparing ohmic contacts for the many types of field-effect transistors now under development for Ge and III–V complementary field-effect transistor technology.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

scholarly journals Large Area Emission in p-Type Polymer-Based Light-Emitting Field-Effect Transistors by Incorporating Charge Injection Interlayers

Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 901
Author(s):  
Gizem Acar ◽  
Muhammad Javaid Iqbal ◽  
Mujeeb Ullah Chaudhry
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Charge Injection ◽  
Limiting Factors ◽  
Hole Injection ◽  
Large Area ◽  
Device Structure ◽  
Light Emitting ◽  
Emission Area ◽  
P Type

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.

scholarly journals Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 187 ◽  
Author(s):  
Kamil Bargieł ◽  
Damian Bisewski ◽  
Janusz Zarębski
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Dynamic Properties ◽  
Modified Model ◽  
Spice Model ◽  
Capacitance Voltage ◽  
Effect Transistor ◽  
Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

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