Anomalously persistent p-type behavior of WSe2 field-effect transistors by oxidized edge-induced Fermi-level pinning

Author(s):  
Tien Dat Ngo ◽  
Min Sup Choi ◽  
Myeongjin Lee ◽  
Fida Ali ◽  
Won Jong Yoo

A technique to form the edge contact in two-dimensional (2D) based field-effect transistors (FETs) has been intensively studied for the purpose of achieving high mobility and also recently overcoming the...

Nanoscale ◽  
2020 ◽  
Vol 12 (16) ◽  
pp. 8883-8889 ◽  
Author(s):  
Ronen Dagan ◽  
Yonatan Vaknin ◽  
Yossi Rosenwaks

Gap states and Fermi level pinning play an important role in all semiconductor devices, but even more in transition metal dichalcogenide-based devices due to their high surface to volume ratio and the absence of intralayer dangling bonds.


2020 ◽  
Vol 10 (8) ◽  
pp. 2754
Author(s):  
Yu Zhang ◽  
Xiong Chen ◽  
Hao Zhang ◽  
Xicheng Wei ◽  
Xiangfeng Guan ◽  
...  

Molybdenum disulfide (MoS2) field-effect transistors (FETs) with four different metallic electrodes (Au,Ag,Al,Cu) of drain-source were fabricated by mechanical exfoliation and vacuum evaporation methods. The mobilities of the devices were (Au) 21.01, (Ag) 23.15, (Al) 5.35 and (Cu) 40.52 cm2/Vs, respectively. Unpredictably, the on-state currents of four devices were of the same order of magnitude with no obvious difference. For clarifying this phenomenon, we calculated the Schottky barrier height (SBH) of the four metal–semiconductor contacts by thermionic emission theory and confirmed the existence of Fermi-level pinning (FLP). We suppose the FLP may be caused by surface states of the semiconductor produced from crystal defects.


2010 ◽  
Vol 645-648 ◽  
pp. 945-948 ◽  
Author(s):  
John Adjaye ◽  
Michael S. Mazzola

The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.


Nanoscale ◽  
2021 ◽  
Author(s):  
Jun-Jie Zhang ◽  
Tariq Altalhi ◽  
Jihui Yang ◽  
Boris I Yakobson

Two-dimensional field effect transistors (2D FETs) with high mobility semiconducting channels and low contact resistance between the semiconducting channel and the metallic electrodes are highly sought components of future electronics....


2001 ◽  
Vol 78 (21) ◽  
pp. 3334-3336 ◽  
Author(s):  
Xiangdong Chen ◽  
Qiqing Ouyang ◽  
Sankaran Kartik Jayanarayanan ◽  
Freek E. Prins ◽  
Sanjay Banerjee

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