scholarly journals A Methodology for Reconstructing DSET Pulses from Heavy-Ion Broad-Beam Measurements

2020 ◽  
Vol 4 (1) ◽  
pp. 15
Author(s):  
Takahiro Makino ◽  
Shinobu Onoda ◽  
Takeshi Ohshima ◽  
Daisuke Kobayashi ◽  
Hirokazu Ikeda ◽  
...  

A table-based method for the estimation of heavy-ion-induced Digital Single Event Transient (DSET) voltage pulse-width in a single logic cell has been developed. The estimation method is based on the actual heavy-ion-induced transient current data in a single metal-oxide-semiconductor field effect transistor (MOSFET) used in the logic cell. The DSET pulse waveform in an inverter is obtained from which the pulse-width was estimated to be 420 ps. This DSET pulse-width value (420 ps) falls within the reasonable range of the DSET pulse-width distribution measured by the self-triggering flip-flop latch chain under heavy-ion irradiation test conditions.

Symmetry ◽  
2019 ◽  
Vol 11 (6) ◽  
pp. 793 ◽  
Author(s):  
Jingyan Xu ◽  
Yang Guo ◽  
Ruiqiang Song ◽  
Bin Liang ◽  
Yaqing Chi

Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.


2008 ◽  
Author(s):  
Asami Hayato ◽  
Toru Tamagawa ◽  
Koji Abe ◽  
Satoshi Nakamura ◽  
Iwahashi Takanori ◽  
...  

2012 ◽  
Vol 717-720 ◽  
pp. 469-472
Author(s):  
Takahiro Makino ◽  
Naoya Iwamoto ◽  
Shinobu Onoda ◽  
Takeshi Ohshima ◽  
Kazutoshi Kojima ◽  
...  

Peak value degradation of heavy-ion induced transient currents in Metal-Oxide-Semiconductor (MOS) capacitors fabricated on n-type and p-type 6H-SiC was observed. The capacitances of MOS capacitors measured during the ion irradiation suggest that the depletion layer width decreased with increasing number of incident ions and was saturated. Since the number of incident ions obtained at the peak current saturation corresponded to that at the saturation of the capacitance, the decrease in peak current can be interpreted in terms of the decrease in the depletion layer width.


2012 ◽  
Vol 48 (3) ◽  
pp. 171 ◽  
Author(s):  
K. Schweiger ◽  
M. Hofbauer ◽  
H. Dietrich ◽  
H. Zimmermann ◽  
K.O. Voss ◽  
...  

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 323 ◽  
Author(s):  
Chang Cai ◽  
Xue Fan ◽  
Jie Liu ◽  
Dongqing Li ◽  
Tianqi Liu ◽  
...  

The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 − 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 − 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.


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