scholarly journals A Novel Low Power 8-Bit Binary Weighted Charge Steering DAC with Integrated Power Supply using CMOS

2020 ◽  
Vol 9 (4) ◽  
pp. 197-203
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Design And Implementation ◽  
Equipment Cost ◽  
Pessimistic Scenario ◽  
Binary Weighted

the design and implementation of binary weighted charge steering DAC architectures is discussed in this paper. Charge steering DAC were designed and successfully implemented in CMOS 90nm and 180nm technology. For bigger planning contrasts there is an exchange off between powerful number of bits, and equipment cost and basic way. Taking everything into account, an 8 piece two fold weighted accuse directing DAC of coordinated force supply was effectively planned in 90 and 180nm CMOS innovation utilizing Cadence apparatuses. As indicated by the reproduction results, the proposed DAC is exceptionally straight with the most pessimistic scenario DNL of 0.99LSB and INL of 0.008LSB, and furthermore has low force utilization esteem 96.36mW

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Added Efficiency ◽  
Microwave Amplifiers

scholarly journals A Low Power AC/DC Interface for Wind-Powered Sensor Nodes

Energies ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1823
Author(s):  
Mohammad Haidar ◽  
Hussein Chible ◽  
Corrado Boragno ◽  
Daniele D. Caviglia
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Energy Harvester ◽  
Optimization Techniques ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Constant Voltage ◽  
Interface Circuit ◽  
Switching Converter ◽  
Input Signals

Sensor nodes have been assigned a lot of tasks in a connected environment that is growing rapidly. The power supply remains a challenge that is not answered convincingly. Energy harvesting is an emerging solution that is being studied to integrate in low power applications such as internet of things (IoT) and wireless sensor networks (WSN). In this work an interface circuit for a novel fluttering wind energy harvester is presented. The system consists of a switching converter controlled by a low power microcontroller. Optimization techniques on the hardware and software level have been implemented, and a prototype is developed for testing. Experiments have been done with generated input signals resulting in up to 67% efficiency for a constant voltage input. Other experiments were conducted in a wind tunnel that showed a transient output that is compatible with the target applications.

scholarly journals Research on anode power supply of low-power Hall thruster

2021 ◽  
Vol 1754 (1) ◽  
pp. 012167
Author(s):  
JIA Hangyu ◽  
QU Chengzhi ◽  
JI Yuhui ◽  
ZHOU Guangrui ◽  
WU Suliang
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Hall Thruster

A calibration-free low-power supply-pushing reduction circuit (SPRC) for LC VCOs

2017 ◽  
Author(s):  
Muhammad Swilam ◽  
Ahmed Naguib ◽  
Brian Dupaix ◽  
Waleed Khalil ◽  
Ayman Fayed
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Calibration Free

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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