scholarly journals Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

2019 ◽  
Vol 9 (2) ◽  
pp. 8-15
Keyword(s):  
Low Power ◽  
Communication Networks ◽  
High Speed ◽  
Average Power ◽  
Memory Cell ◽  
Dielectric Materials ◽  
Content Addressable Memory ◽  
Adiabatic Logic ◽  
Effect Transistor ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) cells are proposed. The adiabatic logic is integrated with the proposed BCAM cells to improve performance. The performance of proposed BCAM cells is presented for various CNTFET parameters such as number of tubes, chirality vector, pitch value, dielectric constant and dielectric materials. It also explores the optimum set of CNTFET parameters for low power and high speed characteristics of the proposed BCAM cells. Simulation results show an improvement in the average power and delay of proposed BCAM cells. The average power of the proposed BCAM cells is in the order of nano watts while the CMOS based BCAM cells is in the order of micro watts. The delay of the proposed BCAM cells is improved by 56.4 %. All simulations are conducted for both CMOS and CNTFET based BCAM cells in HSPICE at 32 nm technology

scholarly journals Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

2019 ◽  
Vol 9 (1) ◽  
pp. 5962-5965
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
High Speed ◽  
Peak Power ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Addressable Memory ◽  
Power Peak ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

scholarly journals Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8203
Author(s):  
Avireni Bhargav ◽  
Phat Huynh
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Average Power ◽  
Propagation Delay ◽  
Approximate Computing ◽  
Effect Transistor ◽  
Developing Area ◽  
Power Delay Product

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

scholarly journals Design of Low Power and High Speed Decoder and Priority Encoder using Carbon Nanotube Field Effect Transistor for Binary Content Addressable Memory Array

2019 ◽  
Vol 8 (4) ◽  
pp. 892-896
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
High Speed ◽  
Peak Power ◽  
Field Effect Transistor ◽  
Average Power ◽  
Average Delay ◽  
Content Addressable Memory ◽  
Effect Transistor ◽  
Priority Encoder

In this paper, design of Positive Feedback Adiabatic Logic (PFAL) based decoder and priority encoder using Carbon Nanotube Field Effect Transistor (CNTFET) for Binary Content Addressable Memory (BCAM) array is presented. The optimum set of CNTFET parameters such as number of tubes, chirality vector, pitch, dielectric constant and dielectric materials for low power and high speed encoder and decoder is used. The performance of proposed decoder and priority encoder is analyzed for average power, peak power and delay. Simulation results show that the proposed circuits outperforms compared to that of CMOS technology based circuits. The average power and peak power of the proposed decoder and priority encoder are in the range of µW while the range of values for CMOS based decoder are mW. The average delay of the proposed decoder is improved by 35.96% compared to that of CMOS based decoder. The average delay of the proposed priority encoder is improved by 30.77% compared to that of CMOS based priority encoder. All simulations are conducted for both CMOS and CNTFET based decoder and Priority encoder in HSPICE at 32 nm technology.

scholarly journals Low Power based Dynamic TSPC D flip flop for High Performance Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 758-762
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Memory Cell ◽  
Research Center ◽  
Short Channel ◽  
Flip Flop ◽  
Force Application ◽  
Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

scholarly journals Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

2008 ◽  
Vol 29 (10) ◽  
pp. 1094-1097 ◽  
Author(s):  
G. Dewey ◽  
M.K. Hudait ◽  
Kangho Lee ◽  
R. Pillarisetty ◽  
W. Rachmady ◽  
...  
Keyword(s):  
Quantum Well ◽  
Low Power ◽  
High Speed ◽  
Carrier Transport ◽  
High Mobility ◽  
Performance Impact ◽  
And Performance ◽  
Low Power Logic

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

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