scholarly journals Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8203
Author(s):  
Avireni Bhargav ◽  
Phat Huynh
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Average Power ◽  
Propagation Delay ◽  
Approximate Computing ◽  
Effect Transistor ◽  
Developing Area ◽  
Power Delay Product

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Maximum Delay ◽  
Average Power Consumption

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

scholarly journals Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Shikha Panwar ◽  
Mayuresh Piske ◽  
Aatreya Vivek Madgula
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Circuits ◽  
Output Node ◽  
Critical Sections

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

scholarly journals The Design of Low-Power High-Speed Two-Level Three Input XOR gate

2020 ◽  
Vol 9 (5) ◽  
pp. 1813-1818
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Signal Frequency ◽  
Xor Gate ◽  
Input Signal Frequency ◽  
Transmission Gates ◽  
Exclusive Or

The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

scholarly journals Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

2019 ◽  
Vol 9 (2) ◽  
pp. 2630-2635
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Low Power Design ◽  
Low Complexity ◽  
Approximate Computing ◽  
New Methodologies ◽  
Power Delay Product ◽  
Booth Encoder ◽  
Complex Multiplier

As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bits, which resulted in a reduction of the power delay product. Approximate computing is a relevant technique for low power and high performance circuits as used in error-tolerant applications. Approximate or inexact computing is an attractive design methodology for low power design but accomplished by loosening up the necessity of precision. It becomes critical to maintain full accuracy to attain reduced power utilization. In this paper, the design of approximate redundant binary (RB) multipliers is studied and modified to build less complex multiplier with Radix-8 modified booth encoding technique to reduce area and complexities of architectures.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

scholarly journals Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
‘Aqilah binti Abdul Tahrim ◽  
Huei Chaeng Chin ◽  
Cheng Siong Lim ◽  
Michael Loong Peng Tan
Keyword(s):  
High Speed ◽  
Average Power ◽  
Full Adder ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Subthreshold Region ◽  
And Performance ◽  
Power Delay Product ◽  
20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

scholarly journals The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

2019 ◽  
Vol 3 (3) ◽  
pp. 19-27
Author(s):  
Mohsen Sadeghi ◽  
Mahya Zahedi ◽  
Maaruf Ali
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Propagation Delay ◽  
Simulation Software ◽  
Low Power Consumption ◽  
Ultra Low Power ◽  
Novel Structure

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

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