Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

scholarly journals Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

2020 ◽  
Vol 2020 ◽  
pp. 1-7
Author(s):  
Mathan Natarajamoorthy ◽  
Jayashri Subbiah ◽  
Nurul Ezaila Alias ◽  
Michael Loong Peng Tan
Keyword(s):  
Power Consumption ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Graphene Nanoribbon ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Sram Design ◽  
Effect Transistor ◽  
Static Noise

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

scholarly journals Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8203
Author(s):  
Avireni Bhargav ◽  
Phat Huynh
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Average Power ◽  
Propagation Delay ◽  
Approximate Computing ◽  
Effect Transistor ◽  
Developing Area ◽  
Power Delay Product

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

scholarly journals A novel design of high performance1-bit adder circuit at deep sub-micron technology

2017 ◽  
Vol 7 (1.1) ◽  
pp. 660
Author(s):  
Venkata Rao Tirumalasetty ◽  
C V. Mohan Krishna ◽  
K Sai Sree Tanmaie ◽  
T Lakshmi Naveena ◽  
Ch Jonathan
Keyword(s):  
Power Consumption ◽  
Average Power ◽  
Full Adder ◽  
Low Delay ◽  
Average Power Consumption ◽  
Good Improvement ◽  
Pass Transistor ◽  
Pass Transistor Logic ◽  
Power Delay Product ◽  
Novel Design

In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.  

scholarly journals The Mixed Logic Style based Low Power and High Speed One-bit Binary adder for SOI Designs AT 32NM Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 361-366
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Full Adder ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Binary adders are the fundamental building blocks to construct Data Processing arithmetic units. A novel one-bit full adder is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the one-bit full adder like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual Voltage Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity and by improving the driving capability. This Mixed logic style provides 83.53% average power consumption and Propagation Delay of 14.02% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of the Full adder logic at different voltages. The 32nm model file is used for MOS transistors

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (3) ◽  
pp. 3037-3045
Author(s):  
M. Naga Gowtham Et.al
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (5) ◽  
pp. 92-100
Author(s):  
M. Naga Gowtham, P.S Hari Krishna Reddy, K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

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