scholarly journals Comparative Analysis in Terms of Power and Delay of the Different Sense Amplifier Topologies

2021 ◽  
Author(s):  
Alok Kumar Mishra ◽  
◽  
Urvashi Chopra ◽  
Vaithiyanathan Dhandapani ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Performance Comparison ◽  
Point Of View ◽  
Sense Amplifier ◽  
Data Line ◽  
Different Types ◽  
Sense Amplifiers ◽  
On Chip ◽  
The Internet Of Things

To read the data from the memory in each of the devices is crucial. In the modern-day VLSI, world need high-speed devices to satisfy the demand for application such as the Internet of Things (IoT) and System on Chip (Soc). We have implemented the different types of existing sense amplifiers to investigate the working and application point of view. Every sense amplifier has its own advantage. Each of the sense amplifiers is focusing basically on the charging and discharging of Bit Line (BL), Bit Line Bar (BLB) in case of Voltage sense and Data Line (DL), Data Line Bar (DLB) in case of current sense. The waveform of the Voltage sense and current sense clearly shown. Performance comparison based on Sensing Delay, Power, and Supply variation at UMC 65nm CMOS technology node using CADENCE Virtuoso tool.

scholarly journals Comparative study of different Sense Amplifiers in 0.18um technology

2013 ◽  
Vol 7 (3) ◽  
pp. 615-619
Author(s):  
Sunil Kumar ◽  
Arun Kr. Chatterjee
Keyword(s):  
Comparative Study ◽  
Power Supply ◽  
Cmos Technology ◽  
Parasitic Capacitance ◽  
Simulation Tools ◽  
Sense Amplifier ◽  
Different Types ◽  
Sense Amplifiers ◽  
Comparative Results

A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiers  are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output of sense amplifier is isolated from the bitline parasitic capacitance then the sensing delay of sense amplifier reduces.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

A LOW POWER AND VARIATION-INSENSITIVE CURRENT-MODE SIGNALING SCHEME

2013 ◽  
Vol 22 (08) ◽  
pp. 1350068
Author(s):  
XINSHENG WANG ◽  
YIZHE HU ◽  
LIANG HAN ◽  
JINGHU LI ◽  
CHENXU WANG ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Current Mode ◽  
Signal Propagation ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Noise Performance ◽  
On Chip ◽  
Variation Tolerance ◽  
Driving Signal

Process and supply variations all have a large influence on current-mode signaling (CMS) circuits, limiting their application on the fields of high-speed low power communication over long on-chip interconnects. A variation-insensitive CMS scheme (CMS-Bias) was offered, employing a particular bias circuit to compensate the effects of variations, and was robust enough against inter-die and intra-die variations. In this paper, we studied in detail the principle of variation tolerance of the CMS circuit and proposed a more suitable bias circuit for it. The CMS-Bias with the proposed bias circuit (CMS-Proposed) can acquire the same variation tolerance but consume less energy, compared with CMS-Bias with the original bias circuit (CMS-Original). Both the CMS schemes were fabricated in 180 nm CMOS technology. Simulation and measured results indicate that the two CMS interconnect circuits have the similar signal propagation delay when driving signal over a 10 mm line, but the CMS-Proposed offers about 9% reduction in energy/bit and 7.2% reduction in energy-delay-product (EDP) over the CMS-Original. Simulation results show that the two CMS schemes only change about 5% in delay when suffering intra-die variations, and have the same robustness against inter-die variations. Both simulation and measurements all show that the proposed bias circuits, employing self-biasing structure, contribute to robustness against supply variations to some extent. Jitter analysis presents the two CMS schemes have the same noise performance.

scholarly journals System-on-chip sensor fusion front-end self-healing design for network-on-chip digital communications

2017 ◽  
Author(s):  
Emmanuel Seaman ◽  
Jason Du
Keyword(s):  
Sensor Fusion ◽  
Data Storage ◽  
Communication Systems ◽  
High Speed ◽  
Process Variations ◽  
Cmos Technology ◽  
Network On Chip ◽  
Cmos Process ◽  
Self Healing ◽  
On Chip

With the ultra-scaling of CMOS technology, high-speed and low-power millimeter-wave communication systems for network-on-chip have been attracting more and more attentions due to the wider bandwidth and higher data rate that can meet the ever-increasing needs for multimedia, massive external data storage, or even biomedical applications. However, from manufacturing’s perspective, the circuits implementations are increasingly susceptible to fabrication process variations with the scaling of CMOS technology, which results in loss of yield rate. To solve this issue, a sensor-fusion solution is proposed in this paper by adding multiple on-chip sensors, including power detectors, temperature sensors, information envelope detectors and related filters, instrumentation amplifiers using a standard CMOS process. These sensors and detectors aim to collect critical system performance and environmental parameters, which will be utilized by a self-healing and optimization algorithm to adjust the state of system components by digitized control knobs.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

2017 ◽  
Vol 64 (10) ◽  
pp. 3979-3985 ◽  
Author(s):  
Jie-Ting Chen ◽  
Chun-Yu Lin ◽  
Ming-Dou Ker
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Protection Device ◽  
Esd Protection ◽  
On Chip

Design of a SoC With High-Speed DDC for Software Radio Receiver

2012 ◽  
Vol 605-607 ◽  
pp. 1875-1879 ◽  
Author(s):  
Jun Deng ◽  
Lin Tao Liu ◽  
Yu Jing Li ◽  
Xiao Zong Huang ◽  
Xu Huang ◽  
...  
Keyword(s):  
High Speed ◽  
Software Radio ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Clock Frequency ◽  
Baseband Signal ◽  
Baseband Signal Processing ◽  
Good Potential ◽  
On Chip

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

scholarly journals Performance Comparison for Spam Detection in Social Media Using Deep Learning Algorithms

2021 ◽  
Vol 12 (1S) ◽  
pp. 193-201
Author(s):  
Rushali Deshmukh, Et. al.
Keyword(s):  
Social Media ◽  
Community Violence ◽  
High Speed ◽  
Personal Data ◽  
Value Added ◽  
Knowledge Bases ◽  
Performance Comparison ◽  
Point Of View ◽  
Spam Detection ◽  
Algorithmic Technique

Social media applications like Twitter, Instagram, Facebook have helped people to connect to each other. This has been eased due to high-speed internet. However, this has invited various spam messages through tweets or Facebook. The sole purpose of such messages is aggregation or exploitation of personal data in terms of finances or medical records, political benefit’s or community violence. This makes spam detection an extreme value-added service. We tend to recommend a 1D CNN algorithmic technique and compare results with variants of CNN and with boosting algorithms. The model is braced with linguistics data in the illustration of the words with the assistance of knowledge-bases such as Word2vec and fast ext. This improves the end to end performance, by providing higher linguistics vector illustration of input testing words. Projected Experimental results show the efficiency of the projected approach from the point of view of accuracy, F1-score and response time.

Broadband sub-THz spectroscopy modules integrated in 65-nm CMOS technology

2017 ◽  
Vol 9 (6) ◽  
pp. 1211-1218 ◽  
Author(s):  
Marion K. Matters-Kammerer ◽  
Dave Van Goor ◽  
Lorenzo Tripodi
Keyword(s):  
Frequency Domain ◽  
Transmission Lines ◽  
High Speed ◽  
Schottky Diodes ◽  
Cutoff Frequency ◽  
Design Procedure ◽  
Cmos Technology ◽  
Thz Spectroscopy ◽  
Non Linear ◽  
On Chip

The design and characterization of a broadband 20–480 GHz continuously tuneable on-chip spectrometer based on non-linear transmission lines in 65-nm CMOS technology is presented. The design procedure of the sampler that detects the ultra-broadband signal from the transmitter in time and frequency domain is described in detail. It consists of a non-linear transmission line, a passive pulse differentiator and a high-speed sample and hold-circuit. The relevance of the layout of the Schottky diodes in the sampler with a maximum RC-cutoff frequency of 430 GHz is described. Time domain and frequency domain measurements are presented to characterize the 480 GHz sampler bandwidth as well as the 3.1 ps sampler rise time. A signal to noise ratio of 90 dB at 100 GHz, 70 dB at 200 GHz and more than 30 dB at 480 GHz is reached. Two implementation of the spectrometer with antennas are presented, one with an on-chip antenna and one in a hybrid package. The antenna-less on-chip implementation of the transmitter and sampler requires no external lenses and is miniaturized to an area of 3 mm2. Future applications include analysis of fluids in microfluidic packages or droplet analysis in bio-medical or pharmaceutical applications.

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