scholarly journals XOR Based Carry Select Adder for Area and Delay

2020 ◽  
Vol 5 (6) ◽  
pp. 1615-1621
Author(s):  
Ramyabanu Bobba ◽  
Pooja Illa
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Design Research ◽  
Logic Gate ◽  
Vlsi Design ◽  
Full Adder ◽  
Low Area ◽  
Carry Select Adder ◽  
Technology Comparison

Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and complexity minimization. The proposed 16-bit carry select adder provides better results compared to the conventional 16-bit carry select adder with Area and delay.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals High Speed and Low Power Consumption by Exploitation using Novel XOR and XNOR Gates

2019 ◽  
Vol 8 (12S) ◽  
pp. 1182-1186
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Full Adder ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Input Noise ◽  
Threshold Voltages ◽  
Output Capacitance

The present paper proposes a high speed and low power consumption by travelling novel XOR and XNOR gates. The present circuit consist optimized power intakeas well asdelay due to smallamount produced capacitance and power dissipation for low short circuit. Here we utilize 6 new hybrid 1 bit full adder circuitthat produces to and fro XOR/XNOR gates. Here the present circuit has its own advantages like rapidity, power consumption and delay in power product, dynamic capability and so on. Here we proposed signals like HSPICE, Cadence simulations for investigating the performance results which are based on 65-nm CMOS process technical models that indicate high speed and power against FA signals. So here we propose a novel new transistor sizing method that optimizes the PDP circuits. The present circuit investigates on various supply terms of variations like threshold voltages, size of transistors, input noise and output capacitance by utilizing numerical computation particle swam optimization algorithm for achieving desired value in optimum PDP with few iterations

scholarly journals AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR

2021 ◽  
Vol 9 (1) ◽  
pp. 159-163
Author(s):  
T. Subhashini, M. Kamaraju, K. Babulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Modern Technology ◽  
Power Reduction ◽  
Flip Flop ◽  
Xor Gate ◽  
Long Run

Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.  

scholarly journals Low power design of ultra wideband PLL using 90 nm CMOS technology

2020 ◽  
Vol 20 (2) ◽  
pp. 727
Author(s):  
Fadhilah Binti Noor Al Amin ◽  
Nabihah Ahmad ◽  
Siti Hawa Ruslan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Vlsi Design ◽  
Electronic System ◽  
Low Power Design ◽  
Cmos Technology ◽  
Ultra Wideband

<span>The rapid growth of the electronic system has become one of the challenges in the high performance of Very Large Scale Integration (VLSI) design and has contributed to the evolution of Phase Locked Loop (PLL) system design as one of the inevitable and significant necessities in the modern days. This design focus on the development of PLL system that can operate at a high performance within the Ultra-Wideband (UWB) frequency but consume low power that may be useful for future device implementation in the communication system. All proposed sub modules of PLL is highly suitable for low power and high speed application as each of them consumes overall power consumption around 2 µW until 1 mW with frequency from 3.1 GHz to 10.6 GHz. All the design architecture, schematic, simulation and analysis are implemented using Synopsys Tool in 90 nm CMOS technology. Through the overall analysis, it can be concluded that this proposed sub modules design of the PLL system has better performance compared to previous work in terms of power consumption and frequency.</span>

scholarly journals HIGH SPEED ADDER USING GDI TECHNIQUE

2020 ◽  
Vol 5 (2) ◽  
pp. 130-136
Author(s):  
Merrin Mary Solomon ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Full Adder ◽  
Low Complexity ◽  
Propagation Delay ◽  
Logic Design ◽  
Reduce Power Consumption

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

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