The Integrated Display System in Aircraft Cockpit Based on FPGA

2014 ◽  
Vol 651-653 ◽  
pp. 911-915
Author(s):  
Jing Gao ◽  
Yin Liang Jia ◽  
Bing Yang Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Random Access ◽  
Display System ◽  
Logic Device ◽  
Access Memory ◽  
Real Time Processing ◽  
Main Research ◽  
Ping Pong ◽  
Integrated Display

The main research object is the graphics generation and display system based on FPGA, the system is mainly used for the integrated display of aircraft cockpit. The display system has the characteristics of large amount of data, real-time processing in the graphics generation. According to the characters, the paper uses programmable logic device due to FPGA has the advantages of high speed, real time. In order to further improve the efficiency of the system, the paper also designs the ping-pong operation of double SSRAM(Synchronous Static Random Access Memory) at the same time. Through the experiment, the system can run well and achieve the desired objectives.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

In Situ Study of Barrier Layers Using Spectroscopic Ellipsometry and Mass Spectroscopy of Recoiled Ions

2000 ◽  
Vol 619 ◽  
Author(s):  
Y. Gao ◽  
A.H. Mueller ◽  
E.A. Irene ◽  
O. Auciello ◽  
A.R. Krauss ◽  
...  
Keyword(s):  
Real Time ◽  
Mass Spectroscopy ◽  
Spectroscopic Ellipsometry ◽  
Nitrogen Concentration ◽  
Random Access ◽  
Copper Interconnects ◽  
Access Memory ◽  
Barrier Layers ◽  
The Stability

ABSTRACTAn in situ study of barrier layers using spectroscopic ellipsometry (SE) and Time-of-Flight (ToF) mass spectroscopy of recoiled ions (MSRI) is presented. First the formation of copper silicides has been observed by real-time SE and in situ MSRI in annealed Cu/Si samples. Second TaSiN films as barrier layers for copper interconnects were investigated. Failure of the TaSiN layers in Cu/TaSiN/Si samples was detected by real-time SE during annealing and confirmed by in situ MSRI. The effect of nitrogen concentration on TaSiN film performance as a barrier was also examined. The stability of both TiN and TaSiN films as barriers for electrodes for dynamic random access memory (DRAM) devices has been studied. It is shown that a combination of in situ SE and MSRI can be used to monitor the evolution of barrier layers and detect the failure of barriers in real-time.

scholarly journals Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 371 ◽  
Author(s):  
Sunhwa Nam ◽  
Kyungwoon Cho ◽  
Hyokyung Bahn
Keyword(s):  
Real Time ◽  
Power Saving ◽  
Random Access ◽  
Random Access Memory ◽  
Voltage Scaling ◽  
Real Time Systems ◽  
Access Memory ◽  
Placement Problem ◽  
Worst Case ◽  
Time Systems

A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%.

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

2006 ◽  
Vol 19 (5) ◽  
pp. S325-S330 ◽  
Author(s):  
Shuichi Nagasawa ◽  
Kenji Hinode ◽  
Tetsuro Satoh ◽  
Yoshihiro Kitagawa ◽  
Mutsuo Hidaka
Keyword(s):  
High Speed ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Flux Quantum ◽  
Access Memory ◽  
Cell Arrays

Nonvolatile Magnetoresistive Random-Access Memory Based on Magnetic Tunnel Junctions

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 818-821 ◽  
Author(s):  
G. Grynkewich ◽  
J. Åkerman ◽  
P. Brown ◽  
B. Butcher ◽  
R.W. Dave ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory ◽  
Static Ram ◽  
New Memory Technology

AbstractMagnetoresistive random-access memory (MRAM) is a new memory technology that is nearing commercialization. MRAM integrates a magnetic tunnel junction (MTJ) device with standard silicon-based microelectronics, resulting in a combination of qualities not found in other memory technologies. For example, MRAM is nonvolatile, has unlimited read and write endurance, and is capable of high-speed read and write operations. In this article, we will describe the fundamentals of an MTJ-based MRAM as well as recent important technology developments in the areas of magnetic materials and memory cell architecture. In addition, we will compare the present and future capabilities of MRAM to those of existing memory technologies such as static RAM and flash memory.

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