A Method for Components Fault Model Building

2012 ◽  
Vol 588-589 ◽  
pp. 156-159
Author(s):  
Rui Liu ◽  
Jun Zhou ◽  
Peng Li
Keyword(s):  
Model Building ◽  
Fault Model ◽  
Fault Models ◽  
Model Function ◽  
Function Unit

This document explains and demonstrates how to build a fault model of any component based on the simulator model. Function unit was considered as the minimum unit when building fault models. The fault model was defined as a uniform style. An example about the control actuator was illustrated. The fault model building method presented in this paper was easy to operate and was of universal appliance.

A Study on Fault Model and Fault-Tolerant Routing for Sensor Networks

2012 ◽  
Vol 182-183 ◽  
pp. 1265-1269
Author(s):  
Zu Ming Xu ◽  
Xiong Fu
Keyword(s):  
Sensor Networks ◽  
Routing Protocols ◽  
Energy Efficient ◽  
Fault Tolerant ◽  
Network Reliability ◽  
Fault Model ◽  
Cross Layer ◽  
Cross Layer Design ◽  
Fault Models ◽  
Energy Aware

Wireless sensor networks require energy-efficient and robust routingprotocols. Most routing protocols for sensor networks try to extendnetwork lifetime by minimizing the energy consumption, but have not taken the network reliability into account. In this paper, we analyze the fault models and propose an ENergy-aware FAult-tolerantRouting scheme, termed as ENFAR. Firstly a link-based uniform fault model is presented, and we adopt a cross-layer design to measurethe transmission delay so as to detect the failed nodes.

scholarly journals Black box delay fault models for non-scan sequential circuits

2018 ◽  
Vol 15 (1) ◽  
pp. 237-256
Author(s):  
Eduardas Bareisa ◽  
Vacius Jusas ◽  
Kestutis Motiejunas ◽  
Liudas Motiejunas ◽  
Rimantas Seinauskas
Keyword(s):  
Fault Model ◽  
Black Box ◽  
Sequential Circuits ◽  
Fault Models ◽  
Delay Fault ◽  
Second Stage ◽  
Transition Faults ◽  
Transition Fault ◽  
Functional Delay ◽  
Two Stages

We presented nine new black box delay fault models for non-scan sequential circuits at the functional level, when the primary inputs and primary outputs are available only. We examined the suggested fault models in two stages. During the first stage of the experiment, we selected the best two fault models for further examination on the base of criterion proposed in the paper. During the second stage, we used the functional delay fault model and two black box delay fault models from the first stage for test selection. The comparison of fault coverages was carried out for transition faults. The obtained results demonstrate that transition fault coverages of tests selected based on proposed black box fault models are similar to coverages of tests selected based on functional delay fault model that uses the inner state of circuit.

scholarly journals Structural complexities and tectonic barriers controlling recent seismic activity of the Pollino area (Calabria-Lucania, Southern Italy) – constraints from stress inversion and 3D fault model building

2021 ◽  
Author(s):  
Daniele Cirillo ◽  
Cristina Totaro ◽  
Giusy Lavecchia ◽  
Barbara Orecchio ◽  
Rita de Nardis ◽  
...  
Keyword(s):  
Seismic Activity ◽  
Model Building ◽  
Fault Model ◽  
P Wave ◽  
Fault System ◽  
Double Difference ◽  
Seismic Sequence ◽  
High Angle ◽  
Time Space ◽  
Seismological Data

Abstract. The integration of field geology and high-resolution seismological data allowed us to reconstruct the 3D Fault Model of the sources which gave rise to the 2010–2014 Pollino seismic sequence. The model is constrained at the surface by structural geological data which provide the true attitude of the single faults and their cross-cut relationships. At depth, the fault geometry was obtained using the distributions of selected high-quality relocated hypocenters. Relocations were carried out through a non-linear Bayloc algorithm, followed by the double-difference relative location method HypoDD, applied to a 3D P-wave velocity model. Geological and seismological data converge in describing an asymmetric active extensional fault system characterized by an E to NNE-dipping low-angle detachment, with its high-angle synthetic splays, and SW- to WSW-dipping, high-angle antithetic faults. The cluster of hypocenters and the peculiar time-space evolution of the seismic activity highlight that two sub-parallel WSW-dipping seismogenic sources, namely the Rotonda-Campotenese and Morano-Piano di Ruggio faults activated during the seismic crisis. By applying to the activated structures the appropriate earthquake-scaling relationships, based on fault length and fault area, we infer that the maximum expected magnitudes calculated using the fault area are the more reliable. We estimated Mw = 6.4 for the Rotonda-Campotenese and Mw = 6.2 for the Morano-Piano di Ruggio deducing that both the faults did not release their seismic potential during the 2010–2014 seismic sequence. The size of the activated patches, reconstructed by projecting on the 3D seismogenic fault planes the early aftershocks of the seismicity clusters, are consistent with the observed magnitude of the associate strongest events. Finally, we point out that the western segment of the Pollino Fault, despite not being presently active, acts as a barrier to the southern propagation of the Rotonda-Campotenese and Morano-Piano di Ruggio faults, limiting their dimensions and seismogenic potential.

Fault Diagnosis for a Three Mass Torsion Oscillator Using a Bank of Fault Models

2008 ◽  
Author(s):  
Joachim Baehr ◽  
Rolf Isermann
Keyword(s):  
Fault Diagnosis ◽  
Fault Model ◽  
Fault Isolation ◽  
Model Parameters ◽  
Equation Approach ◽  
Fault Models ◽  
Sensor Signal ◽  
Torsion Oscillator ◽  
Diagnosis Method

A fault diagnosis method for a three mass torsion oscillator is considered which is subject to different additive faults. By using a bank of fault models three faults of different type are detected, isolated and identified in size and time of occurrence. The bank of fault models is formed by a model of each considered fault. Comparison of simulated fault model outputs and measured signals leads to fault isolation. Fault size and time of occurrence are identified by a parity equation approach and used as fault model parameters. The method is capable to perform the tasks with use of one actuator and one sensor signal. It is shown that common approaches for fault isolation can not be used due to the small number of measured signals.

Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits

2019 ◽  
Vol 28 (12) ◽  
pp. 1950212
Author(s):  
Joyati Mondal ◽  
Bappaditya Mondal ◽  
Dipak Kumar Kole ◽  
Hafizur Rahaman ◽  
Debesh Kumar Das
Keyword(s):  
Emerging Technology ◽  
Fault Model ◽  
Cmos Circuit ◽  
Fault Models ◽  
Toffoli Gate ◽  
Optimal Test ◽  
Test Set ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Reversible Gate

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates. One example of reversible gate is Toffoli gate. A Toffoli gate (also known as [Formula: see text]-CNOT) has two components — the control and the target. Initially, stuck-at fault and other fault models were used for modeling defects in quantum reversible circuits. Later, a new fault model known as missing gate fault model was introduced, which is more effective in capturing the errors in quantum reversible circuit. Boolean Difference is already a known technique to detect stuck-at faults in conventional CMOS circuit. In this paper, Boolean Difference method is applied to derive the test set for detecting each stuck-at fault and missing gate fault in a reversible circuit. Then an optimization algorithm is used to derive an optimal test set, which will detect all possible faults in a circuit. The method is valid also for other fault models.

scholarly journals BLACK-BOX FAULT MODELS

2006 ◽  
Vol 35 (3) ◽  
Author(s):  
Eduardas Bareiša ◽  
Vacius Jusas ◽  
Kęstutis Motiejūnas ◽  
Rimantas Šeinauskas
Keyword(s):  
Test Generation ◽  
Critical Factor ◽  
Fault Model ◽  
Black Box ◽  
Synthesis Process ◽  
Circuit Synthesis ◽  
Fault Models ◽  
Generation Task ◽  
Time To Market ◽  
Time Required

Four black-box fault models are introduced in the paper. The test generation task for the black-box model is more complicated, because possible realizations of the design must be taken into account. However, the time required to generate tests is not very critical factor, because the test generation can be done in parallel with the circuit synthesis process without a prolongation of Time-to-Market. All the proposed fault models were analyzed and investigated experimentally. On the basis of these results, an appropriate fault model responding to the complexity of the problem being solved can be selected.

scholarly journals Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

2021 ◽  
Author(s):  
Raha Abedi
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Cost Effective ◽  
Fault Model ◽  
Reconfigurable Hardware ◽  
Fault Models ◽  
System Complexity ◽  
Synthesis Time ◽  
Cmos Transistor ◽  
Injection Techniques

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

scholarly journals Demystifying Unexpected Silicon Responses through User-Defined Fault Models (UDFM) and Failure Analysis

2021 ◽  
Author(s):  
Subhadip Kundu ◽  
Gaurav Bhargava ◽  
Lesly Endrinal ◽  
Lavakumar Ranganathan
Keyword(s):  
Failure Analysis ◽  
Fault Model ◽  
Test Design ◽  
Fault Models ◽  
Critical Test ◽  
Efficient Manner ◽  
Starting Point ◽  
A Cell ◽  
Diagnosis Algorithm ◽  
Transition Delay

Abstract Failure Analysis (FA) plays an important role during silicon development and yield ramp up, helping identify critical test, design marginality and process issues in a timely and efficient manner. FA techniques typically rely on diagnosis callouts as a starting point for debug. Diagnostic algorithms rely on the error logs collected on production patterns which are generated to detect Stuck-at Faults (SAF) and Transition Delay Faults (TDF). Typically, SAF patterns screen out the static defects and TDF patterns test for transient fails. But often, we see cases where a SAF pattern shmoo is clean but the TDF pattern shmoo is a gross failure indicating a cell-internal static defect missed by the traditional SAF patterns. In this work, we will present our own developed User-Defined Fault Model, which targets cell-internal faults to explain unexpected silicon observations. An added advantage of the work can be seen in improving diagnosis results on the error logs collected using these targeted UDFM patterns. Since UDFM utilizes targeted fault excitation, the diagnosis algorithm results in better callouts. In this paper, we will also propose a custom diagnosis flow using our in-house UDFM to achieve better resolution. Three FA case studies will be presented to showcase the usefulness and effectivity of the proposed methods.

Delay Fault Model Evaluation Using Tester Response Data

2012 ◽  
Author(s):  
Cheng Xue ◽  
R. D. (Shawn) Blanton
Keyword(s):  
Test Generation ◽  
Fault Model ◽  
Delay Testing ◽  
Fault Models ◽  
Delay Test ◽  
Slow Speed ◽  
Delay Fault ◽  
Test Experiment ◽  
Response Data ◽  
Conventional Test

Abstract Most chip producers perform delay testing to detect chips that are affected by defects that adversely affect timing. Several delay fault models have been introduced to guide delay test generation. But similar to static (i.e., slow speed) testing, there is always the question of which fault models are best for ensuring quality. MEasuring Test Effectiveness Regionally (METER) is an approach for evaluating fault model effectiveness. Compared to the conventional test experiment, METER is extremely inexpensive and provides a more thorough evaluation of the quality achievable by a particular fault model. In this work, we describe an extension to METER (called DELAY-METER) that allows the effectiveness of delay fault models to be precisely evaluated. Application of DELAY-METER to the production fail data from an IBM ASIC demonstrates that new and existing delay fault models can be evaluated using conventional tester response data, i.e., data logs collected from production fails through the application of tests generated using conventional fault models.

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