Optimal Space Management Mechanism of Sharable Multi-Channel On-Chip Memory

2012 ◽  
Vol 629 ◽  
pp. 542-547
Author(s):  
Cai Xia Liu ◽  
Xiao Qing Tian ◽  
Zhi Bin Zhang
Keyword(s):  
System Performance ◽  
Allocation Strategy ◽  
Management Mechanism ◽  
Space Management ◽  
Space Allocation ◽  
On Chip ◽  
Utilization Scheme ◽  
Embedded Applications ◽  
Optimal Space ◽  
Model Based Analysis

A kind of shared multi-channel on-chip memory CMP architecture is proposed in this article to efficiently support embedded applications. For the multi-channel on-chip memory being scarce resource, optimal space management mechanism of multi-channel on-chip memory is proposed including automatic space allocation strategy based on application parallelization mapping pattern and optimal space utilization scheme. ILP-model-based analysis of system performance verifies that the proposed optimal space management mechanism can deeply exploit the efficiency of multi-channel on-chip memory to improve system performance.

DSP Memory Allocation Strategy Based on Greedy Algorithm

2014 ◽  
Vol 989-994 ◽  
pp. 1946-1950
Author(s):  
Yan Hong Fan ◽  
Xiao Feng Ma ◽  
Jing Sai Jiang ◽  
Xiao Mei Xu ◽  
Qiu Yun Hao ◽  
...  
Keyword(s):  
Greedy Algorithm ◽  
System Performance ◽  
Low Cost ◽  
Memory Allocation ◽  
Allocation Strategy ◽  
Practical Applications ◽  
Full Speed ◽  
On Chip ◽  
Dsp Systems ◽  
The Greedy Algorithm

In practical applications of DSP systems, DSP chips with limited on-chip RAM resources are often chosen to reduce cost. In this condition, part of the codes has to be stored in FLASH or expanded RAM and thus can not run at full speed. This paper presents a strategy of allocating the on-chip RAMs to obtain the maximum system performance. First, the memory allocation problem is described as the knapsack problem, and then the greedy algorithm is applied. Experimental results show that the overall execution efficiency can be improved by 10% when the on-chip RAMs are rather limited. Therefore, the proposed memory allocation method is efficient for low-cost design to obtain higher performance.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

2014 ◽  
pp. 368-398
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Task Mapping ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
Management Measures ◽  
Mapping Process ◽  
On Chip ◽  
And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

2019 ◽  
Vol 28 (14) ◽  
pp. 1950246
Author(s):  
I. Hariharan ◽  
M. Kannan
Keyword(s):  
System Performance ◽  
Replacement Policy ◽  
Reconfigurable Systems ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Configuration Data ◽  
On Chip ◽  
Time And Energy ◽  
Static Systems

Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology.

scholarly journals An On-Chip Learning Method for Neuromorphic Systems Based on Non-Ideal Synapse Devices

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1946
Author(s):  
Jae-Eun Lee ◽  
Chuljun Lee ◽  
Dong-Wook Kim ◽  
Daeseok Lee ◽  
Young-Ho Seo
Keyword(s):  
Neural Network ◽  
System Performance ◽  
Learning Method ◽  
Ideal Case ◽  
The Neural Network ◽  
Neuromorphic Systems ◽  
Conductance Changes ◽  
Neuromorphic System ◽  
On Chip ◽  
Conductance Level

In this paper, we propose an on-chip learning method that can overcome the poor characteristics of pre-developed practical synaptic devices, thereby increasing the accuracy of the neural network based on the neuromorphic system. The fabricated synaptic devices, based on Pr1−xCaxMnO3, LiCoO2, and TiOx, inherently suffer from undesirable characteristics, such as nonlinearity, discontinuities, and asymmetric conductance responses, which degrade the neuromorphic system performance. To address these limitations, we have proposed a conductance-based linear weighted quantization method, which controls conductance changes, and trained a neural network to predict the handwritten digits from the standard database MNIST. Furthermore, we quantitatively considered the non-ideal case, to ensure reliability by limiting the conductance level to that which synaptic devices can practically accept. Based on this proposed learning method, we significantly improved the neuromorphic system, without any hardware modifications to the synaptic devices or neuromorphic systems. Thus, the results emphatically show that, even for devices with poor synaptic characteristics, the neuromorphic system performance can be improved.

Performance Analysis of MAC in VDL2 Based on OPNET Simulation

2013 ◽  
Vol 385-386 ◽  
pp. 1643-1646
Author(s):  
Lin Gao ◽  
Zhi Jun Wu
Keyword(s):  
System Performance ◽  
Transition Period ◽  
Packet Delay ◽  
Data Link ◽  
Management Mechanism ◽  
Performance Targets ◽  
The Core ◽  
Ground Station ◽  
Data Links ◽  
Performance Research

As one of VHF data links of ATN, VDL2 is publicly recognized as the next generation data-link in the transition period. The paper focused in the performance research of MAC, of which p-CSMA is the core protocol, based on network simulation. As the precondition of simulation, we build VDL2 model in an integral way and realize MAC process modules in both ground station side and aircraft side applying dynamic process and queue management mechanism. In the paper, Performance targets are defined to evaluate the system performance. Through simulation, trends between parameters and targets are reached and the relationships are revealed between packet delay and throughput\ packets strength.

An Efficient Flash Translation Layer for Large Block NAND Flash Devices

2015 ◽  
Vol 24 (09) ◽  
pp. 1550138 ◽  
Author(s):  
Tae-Sun Chung ◽  
Dong-Joo Park ◽  
Jongik Kim
Keyword(s):  
Flash Memory ◽  
System Performance ◽  
Smart Phones ◽  
Large Block ◽  
Nand Flash ◽  
Digital Cameras ◽  
Key Factor ◽  
Mp3 Players ◽  
Flash Translation Layer ◽  
Embedded Applications

Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

scholarly journals Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators

2020 ◽  
Vol 12 (2) ◽  
pp. 116-121
Author(s):  
Rastislav Struharik ◽  
Vuk Vranjković
Keyword(s):  
Power Consumption ◽  
Data Reuse ◽  
Memory Architecture ◽  
Cache Memories ◽  
Data Movement ◽  
Feature Map ◽  
Input Feature ◽  
On Chip ◽  
Memory Resources ◽  
Embedded Applications

Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory architecture, based on the idea of input feature map striping, is proposed, which requires significantly less on-chip memory resources compared to previously proposed solutions. Experiment results show that the proposed cache architecture can reduce on-chip memory size by a factor of 16 or more, while increasing power consumption no more than 15%, compared to some of the previously proposed solutions.

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