Analysis of Low On-Resistance in 4H-SiC Double-Epitaxial MOSFET

2005 ◽  
Vol 483-485 ◽  
pp. 813-816 ◽  
Author(s):  
Shinsuke Harada ◽  
Mitsuo Okamoto ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
Numerical Simulation ◽  
Electric Field ◽  
Gate Oxide ◽  
Type Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Nitrogen Ions

In our previous study, the on-resistance of the SiC-based vertical MOSFET had been reduced in double-epitaxial MOSFET (DEMOSFET). The device exhibited an on-resistance (Rons) of 8.5 mWcm2 with a blocking voltage (Vbr) of 600 V. This study analyzed the characteristics of the DEMOSFET using a numerical simulation. The results showed the trade-off relationship between the specific on-resistance and the blocking characteristics when the concentration of the nitrogen ions increases in the surface of the n-type region between the p-wells. Specially, the specific on-resistance was drastically improved by increasing the concentration of the nitrogen ions. The thick gate oxide on the n-type region between the p-wells had an advantage to suppress the electric field in the gate oxide.

Introduction of Depletion Stopper for Reduction of JFET Resistance for 4H-SiC Trench MOSFET

2015 ◽  
Vol 821-823 ◽  
pp. 761-764 ◽  
Author(s):  
Yasuhiro Kagawa ◽  
Rina Tanaka ◽  
Nobuo Fujiwara ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
...  
Keyword(s):  
Electric Field ◽  
Effective Means ◽  
Gate Oxide ◽  
High Electric Field ◽  
Type Region ◽  
Trade Off ◽  
Parasitic Resistance ◽  
Protection Layer ◽  
P Type

This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (Ron,sp) and the maximum bottom oxide electric field (Eox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication, Ron,sp of the trench-gate SiC-MOSFET with DS is70 % lower than that without DS at a trench depth (dt) of about 1.5 mm. The dtof the trench-gate SiC-MOSFET with DS can be designed 25 % shallower than thatwithout DS at a Ron,sp of about 3.0 mWcm2.Therefore, it can reduce the JFET resistance and allow to shrinkthe trench depth. Optimizing the parametersof DS, the structure having DS is an effective means of reducing the JFETresistance, while reducing Eox by minimizing the depth of the trench.

Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

2017 ◽  
Vol 897 ◽  
pp. 529-532 ◽  
Author(s):  
Luigi di Benedetto ◽  
Gian Domenico Licciardo ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Alfredo Rubino
Keyword(s):  
Figure Of Merit ◽  
Gate Oxide ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Wide Range ◽  
Source Voltage ◽  
Effect Transistor

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

950 Volt 4H-SiC MOSFETs: DC and Transient Performance and Gate Oxide Reliability

2008 ◽  
Vol 600-603 ◽  
pp. 1131-1134 ◽  
Author(s):  
Kevin Matocha ◽  
Zachary Stum ◽  
Steve Arthur ◽  
Greg Dunne ◽  
Ljubisa Stevanovic
Keyword(s):  
Electric Field ◽  
Applied Electric Field ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time To Failure ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Mean Time

SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.

4H-SiC Trench MOSFET with Bottom Oxide Protection

2014 ◽  
Vol 778-780 ◽  
pp. 919-922 ◽  
Author(s):  
Yasuhiro Kagawa ◽  
Nobuo Fujiwara ◽  
Katsutoshi Sugawara ◽  
Rina Tanaka ◽  
Yutaka Fukui ◽  
...  
Keyword(s):  
Electric Field ◽  
Dynamic Characteristics ◽  
Effective Means ◽  
Gate Oxide ◽  
Switching Loss ◽  
Type Region ◽  
Oxide Reliability ◽  
Effective Reduction ◽  
P Type

Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Numerical Simulation of Leakage Current on Conductive Insulator Surface

2019 ◽  
Vol 8 (4) ◽  
pp. 9487-9492
Keyword(s):  
Numerical Simulation ◽  
Electric Field ◽  
Leakage Current ◽  
Method Of Lines ◽  
Electron Attachment ◽  
Negative Ions ◽  
Conduction Current ◽  
Insulator Surface ◽  
Finite Difference Approximations ◽  
Positive Ions

The outdoor insulator is commonly exposed to environmental pollution. The presence of water like raindrops and dew on the contaminant surface can lead to surface degradation due to leakage current. However, the physical process of this phenomenon is not well understood. Hence, in this study we develop a mathematical model of leakage current on the outdoor insulator surface using the Nernst Planck theory which accounts for the charge transport between the electrodes (negative and positive electrode) and charge generation mechanism. Meanwhile the electric field obeys Poisson’s equation. Method of Lines technique is used to solve the model numerically in which it converts the PDE into a system of ODEs by Finite Difference Approximations. The numerical simulation compares reasonably well with the experimental conduction current. The findings from the simulation shows that the conduction current is affected by the electric field distribution and charge concentration. The rise of the conduction current is due to the distribution of positive ion while the dominancy of electron attachment with neutral molecule and recombination with positive ions has caused a significant reduction of electron and increment of negative ions.

Gate Oxide Instability and Lifetime in SiC MOSFETs under a Wide Range of Positive Electric Field Stress

2020 ◽  
Author(s):  
M. Noguchi ◽  
A. Koyama ◽  
T. Iwamatsu ◽  
H. Amishiro ◽  
H. Watanabe ◽  
...  
Keyword(s):  
Electric Field ◽  
Gate Oxide ◽  
Field Stress ◽  
Wide Range

1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

2017 ◽  
Vol 897 ◽  
pp. 497-500 ◽  
Author(s):  
Shinsuke Harada ◽  
Yusuke Kobayashi ◽  
A. Kinoshita ◽  
N. Ohse ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Critical Issue ◽  
High Threshold ◽  
Trade Off ◽  
Negative Gate Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

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