4H-SiC Trench MOSFET with Bottom Oxide Protection

2014 ◽  
Vol 778-780 ◽  
pp. 919-922 ◽  
Author(s):  
Yasuhiro Kagawa ◽  
Nobuo Fujiwara ◽  
Katsutoshi Sugawara ◽  
Rina Tanaka ◽  
Yutaka Fukui ◽  
...  
Keyword(s):  
Electric Field ◽  
Dynamic Characteristics ◽  
Effective Means ◽  
Gate Oxide ◽  
Switching Loss ◽  
Type Region ◽  
Oxide Reliability ◽  
Effective Reduction ◽  
P Type

Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

Introduction of Depletion Stopper for Reduction of JFET Resistance for 4H-SiC Trench MOSFET

2015 ◽  
Vol 821-823 ◽  
pp. 761-764 ◽  
Author(s):  
Yasuhiro Kagawa ◽  
Rina Tanaka ◽  
Nobuo Fujiwara ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
...  
Keyword(s):  
Electric Field ◽  
Effective Means ◽  
Gate Oxide ◽  
High Electric Field ◽  
Type Region ◽  
Trade Off ◽  
Parasitic Resistance ◽  
Protection Layer ◽  
P Type

This paper investigates thereduction of parasitic resistance (JFET resistance) betweenthe p-well and the grounded p-type gate-oxide protection layer (BPW)of a trench-gate SiC-MOSFET. Forming a deeptrench is a way to reducethe JFET resistance, but this consequently leads to high electric field at thebottom oxide. In order to improve the trade-off between the specific on-resistance (Ron,sp) and the maximum bottom oxide electric field (Eox), wenewly developed a trench-gate SiC-MOSFET with an n-type region, named DepletionStopper (DS), formed under the entire p-welllayer. As aresult of fabrication, Ron,sp of the trench-gate SiC-MOSFET with DS is70 % lower than that without DS at a trench depth (dt) of about 1.5 mm. The dtof the trench-gate SiC-MOSFET with DS can be designed 25 % shallower than thatwithout DS at a Ron,sp of about 3.0 mWcm2.Therefore, it can reduce the JFET resistance and allow to shrinkthe trench depth. Optimizing the parametersof DS, the structure having DS is an effective means of reducing the JFETresistance, while reducing Eox by minimizing the depth of the trench.

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

2020 ◽  
Vol 1004 ◽  
pp. 770-775
Author(s):  
Rina Tanaka ◽  
Katsutoshi Sugawara ◽  
Yutaka Fukui ◽  
Hideyuki Hatta ◽  
Hidenori Koketsu ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Short Circuit ◽  
Effective Means ◽  
Gate Oxide ◽  
Device Performance ◽  
High Concentration ◽  
Safe Operation ◽  
Major Drawback ◽  
Oxide Reliability ◽  
Conventional Device

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

950 Volt 4H-SiC MOSFETs: DC and Transient Performance and Gate Oxide Reliability

2008 ◽  
Vol 600-603 ◽  
pp. 1131-1134 ◽  
Author(s):  
Kevin Matocha ◽  
Zachary Stum ◽  
Steve Arthur ◽  
Greg Dunne ◽  
Ljubisa Stevanovic
Keyword(s):  
Electric Field ◽  
Applied Electric Field ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time To Failure ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Reliability ◽  
Blocking Voltage ◽  
Mean Time

SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.

Analysis of Low On-Resistance in 4H-SiC Double-Epitaxial MOSFET

2005 ◽  
Vol 483-485 ◽  
pp. 813-816 ◽  
Author(s):  
Shinsuke Harada ◽  
Mitsuo Okamoto ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda ◽  
Kazuo Arai
Keyword(s):  
Numerical Simulation ◽  
Electric Field ◽  
Gate Oxide ◽  
Type Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Nitrogen Ions

In our previous study, the on-resistance of the SiC-based vertical MOSFET had been reduced in double-epitaxial MOSFET (DEMOSFET). The device exhibited an on-resistance (Rons) of 8.5 mWcm2 with a blocking voltage (Vbr) of 600 V. This study analyzed the characteristics of the DEMOSFET using a numerical simulation. The results showed the trade-off relationship between the specific on-resistance and the blocking characteristics when the concentration of the nitrogen ions increases in the surface of the n-type region between the p-wells. Specially, the specific on-resistance was drastically improved by increasing the concentration of the nitrogen ions. The thick gate oxide on the n-type region between the p-wells had an advantage to suppress the electric field in the gate oxide.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Exploration of heavy ion irradiation effects on gate oxide reliability in power MOSFETs

1995 ◽  
Vol 35 (3) ◽  
pp. 603-608 ◽  
Author(s):  
S.R. Anderson ◽  
R.D. Schrimpf ◽  
K.F. Galloway ◽  
J.L. Titus
Keyword(s):  
Ion Irradiation ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Irradiation Effects ◽  
Power Mosfets ◽  
Heavy Ion Irradiation ◽  
Oxide Reliability

Gate Oxide Instability and Lifetime in SiC MOSFETs under a Wide Range of Positive Electric Field Stress

2020 ◽  
Author(s):  
M. Noguchi ◽  
A. Koyama ◽  
T. Iwamatsu ◽  
H. Amishiro ◽  
H. Watanabe ◽  
...  
Keyword(s):  
Electric Field ◽  
Gate Oxide ◽  
Field Stress ◽  
Wide Range

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

The impact of F contamination induced by the process on the gate oxide reliability

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
The Impact
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