Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

2017 ◽  
Vol 897 ◽  
pp. 529-532 ◽  
Author(s):  
Luigi di Benedetto ◽  
Gian Domenico Licciardo ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Alfredo Rubino
Keyword(s):  
Figure Of Merit ◽  
Gate Oxide ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Wide Range ◽  
Source Voltage ◽  
Effect Transistor

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

scholarly journals Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications

2020 ◽  
Vol 10 (7) ◽  
pp. 2499 ◽  
Author(s):  
Namrata Mendiratta ◽  
Suman Lata Tripathi ◽  
Sanjeevikumar Padmanaban ◽  
Eklas Hossain
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Biomedical Applications ◽  
Field Effect Transistor ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Interface ◽  
Heavily Doped ◽  
Effect Transistor

The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.

Subquarter-micrometer Dual Gate Complementary Metal Oxide Semiconductor Field Effect Transistor with Ultrathin Gate Oxide of 2 nm

1998 ◽  
Vol 37 (Part 1, No. 11) ◽  
pp. 5926-5931
Author(s):  
Masahiro Shimizu ◽  
Takashi Kuroi ◽  
Masahide Inuishi ◽  
Hideaki Arima ◽  
Haruhiko Abe ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Complementary Metal Oxide Semiconductor ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Gate ◽  
Effect Transistor

scholarly journals 3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 659
Author(s):  
Kyuhyun Cha ◽  
Jongwoon Yoon ◽  
Kwangsoo Kim
Keyword(s):  
High Frequency ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Oxide ◽  
Oxide Semiconductor ◽  
Static Characteristics ◽  
Gate Structure ◽  
Effect Transistor ◽  
Switching Characteristics

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

scholarly journals Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Michael Loong Peng Tan
Keyword(s):  
Carbon Nanotube ◽  
Electric Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Unit Area ◽  
Gain Control ◽  
Oxide Semiconductor ◽  
Wide Range ◽  
Effect Transistor ◽  
Long Channel

Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.

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