The Impact of Schottky Barrier Tunneling on SiC-JBS Performance

2009 ◽  
Vol 615-617 ◽  
pp. 667-670 ◽  
Author(s):  
Gary M. Dolny ◽  
Richard L. Woodin ◽  
T. Witt ◽  
J. Shovlin
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
Voltage Drop ◽  
Forward Voltage ◽  
Trade Off ◽  
Practical Applications ◽  
Forward Voltage Drop ◽  
Surface Electric Field ◽  
The Impact ◽  
Barrier Tunneling

The impact of barrier tunneling on SiC-JBS performance is studied both experimentally and theoretically. We show that although the pinch-off effects associated with the JBS structure can significantly suppress the surface electric field, barrier tunneling still dominates the reverse behavior. Barrier tunneling determines the apparent breakdown voltage, as well as the apparent breakdown voltage vs. forward voltage drop trade-off of the JBS diode in practical applications.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 1025-1028 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Robert Callanan ◽  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Voltage Drop ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Collector Current ◽  
Forward Voltage ◽  
Collector Voltage ◽  
Forward Voltage Drop ◽  
Chip Size ◽  
Dc Current

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

Simulation Study for the Structural Cell Design Optimization of 15kV SiC p-Channel IGBTs

2019 ◽  
Vol 963 ◽  
pp. 666-669
Author(s):  
Xiao Li Tian ◽  
Ben Tan ◽  
Yun Bai ◽  
Ji Long Hao ◽  
Cheng Yue Yang ◽  
...  
Keyword(s):  
Numerical Simulations ◽  
Design Optimization ◽  
Simulation Study ◽  
Voltage Drop ◽  
Cell Design ◽  
Forward Voltage ◽  
Trade Off ◽  
Structural Cell ◽  
Blocking Voltage ◽  
Forward Voltage Drop

In this paper, the structural cell design optimization of 15kV 4H-SiC p-channel IGBT is performed. The effects of the parameters of JFET region on the blocking voltage and the forward characteristics are analyzed by numerical simulations. The results indicate that the JFET width and JFET region concentration have an important effect on the performance of IGBTs. Based on the simulation structure in this paper, the optimum JFET width is 10μm, and the optimum JFET concentration is 7×1015cm−3. Meanwhile, they should be carefully designed to achieve the best trade-off between the blocking voltage and the forward voltage drop.

Influence of Trench Design on the Electrical Properties of 650V 4H-SiC JBS Diodes

2019 ◽  
Vol 963 ◽  
pp. 549-552
Author(s):  
Oleg Rusch ◽  
Jonathan Moult ◽  
Tobias Erlbacher
Keyword(s):  
Electrical Properties ◽  
Leakage Current ◽  
Breakdown Voltage ◽  
Voltage Drop ◽  
Electrical Characteristics ◽  
Electrical Field ◽  
Forward Voltage ◽  
Voltage Drops ◽  
Forward Voltage Drop ◽  
Trench Structure

This work presents a design study of customized p+ arrays having influence on the electrical properties of manufactured 4H-SiC Junction Barrier Schottky (JBS) diodes with designated electrical characteristics of 5 A forward and 650 V blocking capabilities. The effect of the Schottky area consuming p+ grid on the forward voltage drop, the leakage current and therefore the breakdown voltage was investigated. A recessed p+ implantation, realized through trench etching before implanting the bottom of the trenches, results in a more effective shielding of the electrical field at the Schottky interface and therefore reduces the leakage current. Customizing the p+ grid array in combination with the trench structure, various JBS diode variants with active areas of 1.69 mm2 were fabricated whereas forward voltage drops of 1.58 V @ 5 A with blocking capabilities up to 1 kV were achieved.

scholarly journals Understanding the Leakage Mechanisms and Breakdown Limits of Vertical GaN-on-Si p+n−n Diodes: The Road to Reliable Vertical MOSFETs

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 445
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Buffolo ◽  
Matteo Borga ◽  
Shuzhen You ◽  
...  
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Temperature Dependent ◽  
Trade Off ◽  
The Road ◽  
Current Voltage ◽  
Gan On Si ◽  
The Impact ◽  
Tcad Simulations

This work investigates p+n−n GaN-on-Si vertical structures, through dedicated measurements and TCAD simulations, with the ultimate goal of identifying possible strategies for leakage and breakdown optimization. First, the dominant leakage processes were identified through temperature-dependent current–voltage characterization. Second, the breakdown voltage of the diodes was modelled through TCAD simulations based on the incomplete ionization of Mg in the p+ GaN layer. Finally, the developed simulation model was utilized to estimate the impact of varying the p-doping concentration on the design of breakdown voltage; while high p-doped structures are limited by the critical electric field at the interface, low p-doping designs need to contend with possible depletion of the entire p-GaN region and the consequent punch-through. A trade-off on the value of p-doping therefore exists to optimize the breakdown.

scholarly journals Mobility Models Based on Forward Current-Voltage Characteristics of P-type Pseudo-Vertical Diamond Schottky Barrier Diodes

Micromachines ◽  
2020 ◽  
Vol 11 (6) ◽  
pp. 598
Author(s):  
Min-Woo Ha ◽  
Ogyun Seok ◽  
Hojun Lee ◽  
Hyun Ho Lee
Keyword(s):  
Schottky Barrier ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Mobility Model ◽  
Mobility Models ◽  
Schottky Barrier Diodes ◽  
Forward Voltage ◽  
Forward Voltage Drop ◽  
P Type

Compared with silicon and silicon carbide, diamond has superior material parameters and is therefore suitable for power switching devices. Numerical simulation is important for predicting the electric characteristics of diamond devices before fabrication. Here, we present numerical simulations of p-type diamond pseudo-vertical Schottky barrier diodes using various mobility models. The constant mobility model, based on the parameter μconst, fixed the hole mobility absolutely. The analytic mobility model resulted in temperature- and doping concentration-dependent mobility. An improved model, the Lombard concentration, voltage, and temperature (CVT) mobility model, considered electric field-dependent mobility in addition to temperature and doping concentration. The forward voltage drop at 100 A/cm2 using the analytic and Lombard CVT mobility models was 2.86 and 5.17 V at 300 K, respectively. Finally, we used an empirical mobility model based on experimental results from the literature. We also compared the forward voltage drop and breakdown voltage of the devices, according to variations in p- drift layer thickness and cathode length. The device successfully achieved a low specific on-resistance of 6.8 mΩ∙cm2, a high breakdown voltage of 1190 V, and a high figure-of-merit of 210 MW/cm2.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Comparison of the Forward Voltage Drop of Si and SiC High Voltage Diodes

2014 ◽  
Vol 64 (7) ◽  
pp. 223-236 ◽  
Author(s):  
T. Gachovska ◽  
J. L. Hudgins
Keyword(s):  
High Voltage ◽  
Voltage Drop ◽  
Forward Voltage ◽  
Forward Voltage Drop

scholarly journals 10 kV Silicon Carbide PiN Diodes—From Design to Packaged Component Characterization

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4566 ◽  
Author(s):  
Asllani ◽  
Morel ◽  
Phung ◽  
Planson
Keyword(s):  
Silicon Carbide ◽  
Leakage Current ◽  
Voltage Drop ◽  
Forward Bias ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Pulse Switching ◽  
Turn On ◽  
Forward Voltage Drop ◽  
Fabrication And Characterization

This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.

Characterization and Comparison of 4H-SiC(1120) and 4H-SiC(0001) 8° Off-Axis Substrates and Homoepitaxial Films

2004 ◽  
Vol 815 ◽  
Author(s):  
S.M. Bishop ◽  
E.A. Preble ◽  
C. Hallin ◽  
A. Henry ◽  
W. Sarney ◽  
...  
Keyword(s):  
Voltage Drop ◽  
Stacking Faults ◽  
Separation Distance ◽  
Full Width ◽  
Forward Voltage ◽  
Hydrogen Etching ◽  
X Ray ◽  
Transmission Electron ◽  
Forward Voltage Drop ◽  
Film Substrate

AbstractHomoepitaxial films of 4H-SiC(1120) and 8° off-axis 4H-SiC(0001) have been grown and characterized. The number of domains and the range of full-width half-maxima values of the x-ray rocking curves of the [1120]-oriented wafers were smaller than the analogous values acquired from the (0001) materials. Hydrogen etching of the former surface for 5 and 30 minutes reduced the RMS roughness from 0.52 nm to 0.48 nm and to 0.28 nm, respectively; the RMS roughness for a 30 μm (1120) film was 0.52 nm. Micropipes in the substrates did not thread beyond the film-substrate interface. The separation distance between stacking faults was determined to be 10 μm by transmission electron microscopy. Hall mobilities and carrier concentrations of 12,200 cm2/Vs and 3.1×1014 cm−3 and 800 cm2/Vs and 7.4×1014 cm−3 were measured at 100°K and 300°K, respectively. Photoluminescence indicated high purity. 4H-SiC(1120) PiN devices exhibited average blocking voltages to 1344 V and a minimum average forward voltage drop of 3.94 V.

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