Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

2015 ◽  
Vol 821-823 ◽  
pp. 480-483 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Gate Oxides ◽  
Mos Structure ◽  
Mos Devices ◽  
Inversion Channel ◽  
And Inversion ◽  
Thermally Grown

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

Electrical Characterization of MOS Structures with Deposited Oxides Annealed in N2O or NO

2009 ◽  
Vol 615-617 ◽  
pp. 521-524 ◽  
Author(s):  
Michael Grieb ◽  
Masato Noborio ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Constant Current ◽  
Electrical Characteristics ◽  
Channel Mobility ◽  
Thermally Grown Oxides ◽  
Mos Devices ◽  
Mos Structures ◽  
Thermally Grown

In this work, the electrical characteristics and the reliability of 80nm thick deposited oxides annealed in NO and N2O on the 4H-SiC Si-face for gate oxide application in MOS devices is analyzed by C-V, I-V measurements and by constant current stress. Compared to thermally grown oxides, the deposited oxides annealed in N2O or NO showed improved electrical properties. Dit-values lower than 1011cm-2eV-1 have been achieved for the NO sample. The intrinsic QBD-values of deposited and annealed oxides are one order of magnitudes higher than the highest values reported for thermally grown oxides. Also MOSFETS were fabricated with a channel mobility of 20.05 cm2/Vs for the NO annealed deposited oxide. Furthermore annealing in NO is preferred to annealing in N2O regarding µFE- and QBD-values.

How Small Is Too Small ? Understanding The Electronic Structure Of Atomic-Scale Transistors

1999 ◽  
Vol 5 (S2) ◽  
pp. 120-121
Author(s):  
D. A. Muller ◽  
T. Sorsch ◽  
S. Moccio ◽  
F. H. Baumann ◽  
K. Evans-Lutterodt ◽  
...  
Keyword(s):  
Electronic Structure ◽  
Electrical Properties ◽  
Thermal Oxidation ◽  
Electronic Devices ◽  
Local Environment ◽  
Gate Oxide ◽  
Atomic Scale ◽  
Gate Oxides ◽  
Bulk Properties ◽  
Commercial Use

The transistors planned for commercial use ten years from now in many electronic devices will have gate lengths shorter than 130 atoms, gate oxides thinner than 1.2 nm of SiO2 and clock speeds in excess of 10 GHz. It is now technologically possible to produce such transistors with gate oxides only 5 silicon atoms thick[l]. Since at least two of those 5 atoms are not in a local environment similar to either bulk Si or bulk SiO2, the properties of the interface are responsible for a significant fraction of the “bulk” properties of the gate oxide. However the physical (and especially their electrical) properties of the interfacial atoms are very different from .bulk Si or bulk SiO2. Further, roughness on an atomic scale can alter the leakage current by orders of magnitude.In our studies of such devices, we found that thermal oxidation tends to produce Si/SiO2 interfaces with 0.1-0.2 nm rms roughness.

Characterization of Nitrided Gate Oxide Formed by RTP for SiC MOSFET Application

2011 ◽  
Vol 324 ◽  
pp. 221-224 ◽  
Author(s):  
Aurore Constant ◽  
Philippe Godignon
Keyword(s):  
Gate Oxide ◽  
Breakdown Field ◽  
Gate Oxides ◽  
Furnace Process ◽  
Surface Pretreatment ◽  
Channel Mobility ◽  
Conventional Furnace ◽  
The One

Gate oxides for SiC lateral MOSFETs have been formed in N2O by rapid thermal processing (RTP) as an alternative to the conventional furnace process. This innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to a standard oxidation, but also to produce oxide layers with quality comparable to the one grown in a conventional furnace. Moreover, a significant improvement of the oxide quality and MOSFET performance is observed when performing in-situ a H2 anneal prior to oxidation as surface pretreatment. The channel mobility and the breakdown field of the gate oxide are considerably increased.

TXRF Characterization of Trace Metal Contamination in Thin Gate Oxides

1992 ◽  
Vol 259 ◽  
Author(s):  
R. S. Hockett ◽  
Diane Hymes
Keyword(s):  
Metal Contamination ◽  
Gate Oxide ◽  
Silicon Substrates ◽  
Qualitative Information ◽  
Gate Oxides ◽  
Quantitative Estimates ◽  
Oxide Reliability ◽  
First Time ◽  
Non Destructive

ABSTRACTMetal contamination on the surface of silicon substrates before gate oxidation is known to affect gate oxide reliability. For the first time this study presents a non-destructive, analytical measurement of transition metals in an 8nm gate oxide grown by a 920 °C-10min-dry oxidation of an intentionally contaminated silicon surface. The TECHNOS TREX 610 TXRF anglescan of the gate oxide provides qualitative information on the location of the metals. The data indicate the Fe is on or in the oxide, the Cu is below the oxide, the Zn is on the oxide, and the Ni may be both in the oxide and below the oxide layer. In addition, quantitative estimates from the TXRF data indicate that all the original Fe and Cu are present, while only portions of Zn and Ni are detected after the oxidation.

Implementation of Sub-Resolvable Features for Precise Electrical Characterization of SiC Gate Oxide Parameters

2012 ◽  
Vol 717-720 ◽  
pp. 797-800
Author(s):  
J. Jay McMahon ◽  
Liang Chun Yu ◽  
Jody Fronheiser ◽  
J.T. Elson ◽  
Roger Kovalec ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Screening Tests ◽  
Compensation Mechanism ◽  
Gate Oxides ◽  
Attractive Option ◽  
Van Der Pauw ◽  
Similar Yield

We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.

Novel Approach for Improving Interface Quality of 4H-SiC MOS Devices with UV Irradiation and Subsequent Thermal Annealing

2013 ◽  
Vol 740-742 ◽  
pp. 741-744 ◽  
Author(s):  
Heiji Watanabe ◽  
Daisuke Ikeguchi ◽  
Takashi Kirino ◽  
Shuhei Mitani ◽  
Yuki Nakano ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Thermal Annealing ◽  
Uv Irradiation ◽  
Uv Light ◽  
Interface State ◽  
State Density ◽  
Mos Devices ◽  
Novel Approach ◽  
Subsequent Thermal Annealing ◽  
Thermally Grown

We report on the harmful impact of ultraviolet (UV) light irradiation on thermally grown SiO2/4H-SiC(0001) structures and its use in subsequent thermal annealing for improving electrical properties of SiC-MOS devices. As we previously reported [1], significant UV-induced damage, such as positive flatband voltage shift and hysteresis in capacitance-voltage curves as well as increased interface state density, was observed for SiC-MOS devices with thermally grown oxides. Interestingly, the subsequent annealing of damaged SiO2/SiC samples resulted in superior electrical properties to those for untreated (fresh) devices. These findings imply that UV irradiation of the SiO2/SiC structure is effective for eliciting pre-existing carbon-related defects and transforming them into a simple configuration that can be easily passivated by thermal treatment.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

scholarly journals Heavy-ion RBS characterization of multilayer TiNx-SiO2-Si structures

2020 ◽  
Vol 9 ◽  
pp. 315
Author(s):  
X. Aslanoglou ◽  
E. Evangelou ◽  
N. Konofaos ◽  
Ch. Dimitriades ◽  
E. Kossionides ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Heavy Ion ◽  
Electrical Performance ◽  
Multilayer Structures ◽  
Mos Devices

Multilayer structures consisting of TiNx-SiO2-Si layers operating as MOS devices were constructed and tested for their electrical properties. RBS measurements were performed for the characterization of the structure of the devices. The results show a correlation between the structure found by RBS and the electrical performance of the devices.

Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology

2000 ◽  
Author(s):  
Song Zhigang ◽  
Loh Sock Khim ◽  
Shailesh Redkar
Keyword(s):  
Random Access ◽  
Gate Oxide ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Emission Analysis ◽  
Gate Oxides ◽  
Mos Devices ◽  
Voltage Contrast ◽  
Metal Layers

Abstract With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.

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