Nondestructive and Local Evaluation of SiO2/SiC Interface Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2016 ◽  
Vol 858 ◽  
pp. 469-472 ◽  
Author(s):  
Norimichi Chinone ◽  
R. Kosugi ◽  
Yasunori Tanaka ◽  
Shinsuke Harada ◽  
Hajime Okumura ◽  
...  
Keyword(s):  
High Spatial Resolution ◽  
Interface State ◽  
Higher Order ◽  
State Density ◽  
Strong Correlations ◽  
Interface Quality ◽  
Nonlinear Dielectric ◽  
Spatially Inhomogeneous ◽  
Capacitance Voltage ◽  
Sic Wafer

SiO2/SiC interface was investigated by using super-higher-order (SHO) scanning nonlinear dielectric microscopy (SNDM) with high spatial resolution. Comparison of non-oxidized and thermally oxidized 4H-SiC wafer (Si-face) revealed that only 5 min oxidation makes the interface quality spatially inhomogeneous. Next four SiC wafers treated under different post oxidation annealing (POA) conditions in NO ambient (three “with” and one “without” POA) were also compared. Using SHO-SNDM, local capacitance-voltage (C-V) curves were obtained. The local C-V curve obtained in sample with POA was more close to ideal C-V curve compared to the C-V curves obtained in the sample without POA. In addition, two-dimensional normalized SNDM images taken on the four SiC wafers were observed, which showed that the spatial deviation of interface state was reduced by the POA treatment. Moreover, standard deviations s of the normalized SNDM images were calculated. Then, very strong correlations between σ and interface-state density Dit as well as channel electron mobility μFE were observed.

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Interface Quality ◽  
Channel Mobility ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Post Deposition ◽  
Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

The Limits of Post Oxidation Annealing in NO

2010 ◽  
Vol 645-648 ◽  
pp. 693-696 ◽  
Author(s):  
John Rozen ◽  
Xing Guang Zhu ◽  
Ayayi Claude Ahyi ◽  
John R. Williams ◽  
Leonard C. Feldman
Keyword(s):  
Nitrogen Content ◽  
Oxidation Rate ◽  
Interface State ◽  
State Density ◽  
Annealing Process ◽  
Interface State Density ◽  
Interface Quality

We report on the benefits and the shortcomings of the NO annealing process following observations made on capacitors and transistors with various nitrogen densities at the SiO2/SiC interface. While NO annealing leads to a progressively lower interface state density and higher inversion mobility, consistent with Coulomb-limited transport, MOSFET properties are still limited by the relatively poor interface quality. Moreover, NO induces a large amount of hole traps in the oxide. We establish that these properties are not related to the oxidation rate and we discuss them in terms of the nitrogen content.

Low- and High-Frequency C–V Characteristics of Au/n-GaN/n-GaAs

2018 ◽  
Vol 18 (06) ◽  
pp. 1850039
Author(s):  
Abderrezzaq Ziane ◽  
Mohamed Amrani ◽  
Abdelaziz Rabehi ◽  
Zineb Benamara
Keyword(s):  
Schottky Diode ◽  
High Frequency ◽  
High Vacuum ◽  
Low Frequency ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Ultra High Vacuum ◽  
Active Nitrogen ◽  
Capacitance Voltage

Au/GaN/GaAs Schottky diode created by the nitridation of n-GaAs substrate which was exposed to a flow of active nitrogen created by a discharge source with high voltage in ultra-high vacuum with two different thicknesses of GaN layers (0.7[Formula: see text]nm and 2.2[Formula: see text]nm), the I–V and capacitance–voltage (C–V) characteristics of the Au/n-GaN/n-GaAs structures were studied for low- and high-frequency at room temperature. The measurements of I–V of the Au/n-GaN/n-GaAs Schottky diode were found to be strongly dependent on bias voltage and nitridation process. The electrical parameters are bound by the thickness of the GaN layer. The capacitance curves depict a behavior indicating the presence of interface state density, especially in the low frequency. The interface states density was calculated using the high- and low-frequency capacitance curves and it has been shown that the interface states density decreases with increasing of nitridation of the GaAs.

In-Situ Etch to Improve Chemical Beam Epitaxy Regrown AlgaAs/GaAs Interfaces for HBT Applications

1996 ◽  
Vol 448 ◽  
Author(s):  
Y.M. Hsin ◽  
N. Y. Li ◽  
C. W. Tu ◽  
P. M. Asbeck
Keyword(s):  
Etching Rate ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Chemical Beam Epitaxy ◽  
Capacitance Voltage ◽  
Substrate Temperatures ◽  
Etching Effect

AbstractWe have studied the etching effect of AlxGa1-xAs (0≤ x ≤ 0.5) by trisdimethylaminoarsenic (TDMAAs) at different substrate temperatures, and the quality of the resulting etched/regrown GaAs interface. We find that the etching rate of AlxGa1-x As decreases with increasing Al composition, and the interface trap density of the TDMAAs etched/regrown interface can be reduced by about a factor of 10 as deduced from capacitance-voltage carrier profiles. A smooth surface morphology of GaAs with an interface state density of 1.4×l011 cm−2 can be obtained at a lower in-situ etching temperature of 550°C. Moreover, by using this in-situ etching the I-V characteristics of regrown p-n junctions of Al0.35Ga0.65As/Al0.25Ga0.75As and Al0.35Ga0.65As/GaAs can be improved.

Improved Field Effect Mobility in Si-Face 4H-SiC MOSFETs with a Deposited SiNx Interface Layer

2019 ◽  
Vol 963 ◽  
pp. 469-472 ◽  
Author(s):  
Teruaki Kumazawa ◽  
Mitsuo Okamoto ◽  
Miwako Iijima ◽  
Yohei Iwahashi ◽  
Shinji Fujikake ◽  
...  
Keyword(s):  
Field Effect ◽  
Atomic Layer ◽  
Interface Layer ◽  
Interface State ◽  
State Density ◽  
Field Effect Mobility ◽  
Optimal Thickness ◽  
Interface Quality ◽  
Mos Devices ◽  
Layer Deposition

The SiO2/SiC interface quality has a significant effect on the performance of 4H-SiC MOS devices. The introduction of nitrogen to the SiO2/SiC interface is a well-known method for reducing the interface state density (Dit). In this study, we introduced nitrogen to the SiO2/SiC interface by forming SiNx films using atomic layer deposition (ALD) and thus improved the interface quality. O2 annealing with a SiNx interface layer of optimal thickness enhanced the field effect mobility.

Capacitance-Voltage and Interface State Density Characteristics of GaAs and In0.53Ga0.47As MOS Capacitors Incorporating a PECVD Si3N4 Dielectric

2019 ◽  
Vol 35 (3) ◽  
pp. 415-430 ◽  
Author(s):  
Eamon O'Connor ◽  
Vladimir Djara ◽  
Scott Monaghan ◽  
Paul Hurley ◽  
Karim Cherkaoui
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Capacitance Voltage

scholarly journals Barrier Modification by Methyl Violet Organic Dye Molecules of Ag/P-Inp Structures

2016 ◽  
Vol 2 (3) ◽  
pp. 7 ◽  
Author(s):  
Ömer Güllü
Keyword(s):  
Barrier Height ◽  
Methyl Violet ◽  
Electrical Characterization ◽  
Interface State ◽  
State Density ◽  
Mis Structure ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Mis Diode

This work includes fabrication and electrical characterization of Metal/Interlayer/Semiconductor (MIS) structures with methyl violet organic film on p-InP wafer. Metal(Ag)/ Interlayer (methyl violet =MV)/Semiconductor(p-InP) MIS structure presents a rectifying contact behavior. The values of ideality factor (n) and barrier height (BH) for the Ag/MV/p-InP MIS diode by using the current-voltage (I-V) measurement have been extracted as 1.21 and 0.84 eV, respectively. It was seen that the BH value of 0.84 eV calculated for the Ag/MV/p-InP MIS structure was significantly higher than the value of 0.64 eV of Ag/p-InP control contact. This situation was ascribed to the fact that the MV organic interlayer increased the effective barrier height by influencing the space charge region of inorganic semiconductor. The values of diffusion potential and barrier height for the Ag/MV/p-InP MIS diode by using the capacitance-voltage (C-V) measurement have been extracted as 1.21 V and 0.84 eV, respectively. The interface-state density of the Ag/MV/p-InP structure was seen to change from 2.57×1013 eV-1cm-2 to 2.19×1012 eV-1cm-2.

The Effect of Silicide Formation on the Electrical Properties of Gate Oxides

1992 ◽  
Vol 260 ◽  
Author(s):  
J. P. Gambino ◽  
B. Cunningham ◽  
D. A. Buchanan
Keyword(s):  
Gate Oxide ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Rapid Thermal Anneal ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Oxide Breakdown ◽  
Current Voltage ◽  
Capacitance Voltage

ABSTRACTCoSi2, or TiSi2 formation on gate polysilicon can degrade the current-voltage and capacitance-voltage characteristics of MOS capacitors. Degradation of the gate oxide breakdown field is much more severe for capacitors with TiSi2 than for those with COSi2 TEM reveals evidence for a reaction at the interface between TiSi2 and SiO2, whereas there is no observable reaction between COSi2 and SiO2- The low breakdown fields for devices with TiSi2 may be due to thinning of the gate oxide by the interfacial reaction or mechanical deformation. A high density of electron traps and a small reduction in the breakdown field is observed when COSi2 contacts the gate, possibly due to a compressive stress in the oxide exerted by the suicide. In addition, an increase in the interface state density at the Si-SiO2 interface is seen for all samples exposed to a rapid thermal anneal (RTA) at 800°C, possibly due to the release of H from dangling bonds.

Investigation of Interface State Density with Varied SiO2 Thickness in La2O3/SiO2/4H-SiC MOS Capacitors

2016 ◽  
Vol 858 ◽  
pp. 689-692 ◽  
Author(s):  
Yu Cheng Wang ◽  
Yu Ming Zhang ◽  
Ren Xu Jia
Keyword(s):  
Photoelectron Spectroscopy ◽  
Lattice Mismatch ◽  
Atomic Layer ◽  
Interface State ◽  
Carbon Cluster ◽  
State Density ◽  
Oxide Semiconductor ◽  
Interface Quality ◽  
Mos Capacitors ◽  
Layer Deposition

SiO2 with varying thickness (0, 4.45, and 8.05 nm) were grown on n type 4H-SiC epilayer by thermal oxidation and La2O3 were stacked on them using atomic layer deposition (ALD). The La2O3/SiO2/4H-SiC metal-oxide-semiconductor (MOS) capacitors were analyzed by X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) measurements. C-V curves show that introducing an ultrathin SiO2 can reduce the effect of lattice mismatch of La2O3/4H-SiC structure and then improve interface property. However, the interface quality is reduced as SiO2 was grown thicker. XPS data show that more carbon cluster remains at the interfacial between SiO2 and 4H-SiC as the oxidation time increases.

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